STE10/100A STMicroelectronics, STE10/100A Datasheet - Page 5

• Manufacturer Part Number: STE10/100A
• Description: IC CTRLR PCI ETHERNET 128-PQFP
• Manufacturer: STMicroelectronics

Specifications of STE10/100A

• Controller Type: Ethernet Controller, 10Base-T
• Interface: PCI
• Voltage - Supply: 3.14 V ~ 3.46 V
• Current - Supply: 130mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-3663

STE10/100A
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Detailed features
FIFO
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PCI interface
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EEPROM/Boot ROM interface
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MAC/physical
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Provides independent transmission and receiving FIFOs, each 2k bytes long
Pre-fetches up to two transmit packets to minimize inter frame gap (IFG) to 0.96us
Retransmits collided packet without reload from host memory within 64 bytes.
Automatically retransmits FIFO under-run packet with maximum drain threshold until
3rd time retry failure threshold of next packet.
Provides 32-bit PCI bus master data transfer
Supports PCI clock with frequency from 0Hz to 33MHz
Supports network operation with PCI system clock from 20MHz to 33MHz
Provides performance meter and PCI bus master latency timer for tuning the threshold
to enhance the performance
Provides burst transmit packet interrupt and transmit/receive early interrupt to reduce
host CPU utilization
As bus master, supports memory-read, memory-read-line, memory-read-multiple,
memory-write, memory-write-and-invalidate command
Supports big or little endian byte ordering
Provides writable flash ROM and EPROM as boot ROM, up to 128Kbit
Provides PCI to access boot ROM by byte, word, or double word
Re-writes flash boot ROM through I/O port by programming register
Provides serial interface for read/write 93C46 EEPROM
Automatically loads device ID, vendor ID, subsystem ID, subsystem vendor ID,
maximum-latency, and minimum-grand from the 64 byte contents of 93C46 after PCI
reset de-asserted
Integrates the complete set of physical layer 100BASE-TX and 10BASE-T functions
Provides full-duplex operation in both 100Mbps and 10Mbps modes
Provides auto-negotiation (NWAY) function of full/half duplex operation for both 10 and
100 Mbps
Provides MLT-3 transceiver with DC restoration for base-line wander compensation
Provides transmit wave-shaper, receive filters, and adaptive equalizer
Provides MAC and transceiver (TXCVR) loop-back modes for diagnostic
Built-in stream cipher scrambler/ de-scrambler and 4B/5B encoder/decoder
Supports external transmit and receive transformer with 1:1 turn ratio
Overview
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