DS21FF42 Maxim Integrated Products, DS21FF42 Datasheet - Page 88

• Manufacturer Part Number: DS21FF42
• Description: IC FRAMER T1 4X4 16CH 300-BGA
• Manufacturer: Maxim Integrated Products

Specifications of DS21FF42

• Controller Type: T1 Framer
• Interface: Parallel/Serial
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 300mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 300-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

INSTRUCTION CODES FOR THE DS21352/552 IEEE 1149.1 ARCHITECTURE
Table 22-1
Sample/Preload
A mandatory instruction for the IEEE 1149.1 specification. This instruction supports two functions. The
digital I/Os of the DS21Q42 can be sampled at the boundary scan register without interfering with the
normal operation of the device by using the Capture-DR state. SAMPLE/PRELOAD also allows the
DS21Q42 to shift data into the boundary scan register via JTDI using the Shift-DR state.
Extest
EXTEST allows testing of all interconnections to the DS21Q42. When the EXTEST instruction is
latched in the instruction register, the following actions occur. Once enabled via the Update-IR state, the
parallel outputs of all digital output pins will be driven. The boundary scan register will be connected
between JTDI and JTDO. The Capture-DR will sample all digital inputs into the boundary scan register.
Bypass
When the BYPASS instruction is latched into the parallel instruction register, JTDI connects to JTDO
through the 1-bit bypass test register. This allows data to pass from JTDI to JTDO not affecting the
device’s normal operation.
Idcode
When the IDCODE instruction is latched into the parallel instruction register, the Identification Test
register is selected. The device identification code will be loaded into the Identification register on the
rising edge of JTCLK following entry into the Capture-DR state. Shift-DR can be used to shift the
identification code out serially via JTDO. During Test-Logic-Reset, the identification code is forced into
the instruction register’s parallel output. The ID code will always have a ‘1’ in the LSB position. The
next 11 bits identify the manufacturer’s JEDEC number and number of continuation bytes followed by 16
bits for the device and 4 bits for the version. See Table 23-2. Table 23-3 lists the device ID codes for the
DS21Q42 and DS21Q44 devices.
SAMPLE/PRELOAD
BYPASS
EXTEST
CLAMP
HIGHZ
IDCODE
Instruction
Boundary Scan
Bypass
Boundary Scan
Boundary Scan
Boundary Scan
Device Identification
Selected Register
88 of 114
Instruction Codes
010
111
000
011
100
001