DS21FF42 Maxim Integrated Products, DS21FF42 Datasheet - Page 58

• Manufacturer Part Number: DS21FF42
• Description: IC FRAMER T1 4X4 16CH 300-BGA
• Manufacturer: Maxim Integrated Products

Specifications of DS21FF42

• Controller Type: T1 Framer
• Interface: Parallel/Serial
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 300mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 300-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

TIR1/TIR2/TIR3: TRANSMIT IDLE REGISTERS (Address=3C to 3E Hex)
[Also used for Per–Channel Loopback]
NOTE:
If CCR4.0=1, then a zero in the TIRs implies that channel data is to be sourced from TSER and a one
implies that channel data is to be sourced from the output of the receive side framer (i.e., Per–Channel
Loopback; see Figure 6–1).
TIDR: TRANSMIT IDLE DEFINITION REGISTER (Address=3F Hex)
15.1.2 Per–Channel Code Insertion
The second method involves using the Transmit Channel Control Registers (TCC1/2/3) to determine
which of the 24 T1 channels should be overwritten with the code placed in the Transmit Channel
Registers (TC1 to TC24). This method is more flexible than the first in that it allows a different 8–bit
code to be placed into each of the 24 T1 channels.
(MSB)
CH16
CH24
TIDR7
(MSB)
CH8
SYMBOL
SYMBOL
CH1 - 24
TIDR7
TIDR0
CH15
CH23
CH7
TIDR6
POSITION
TIR1.0 - 3.7
POSITION
CH14
CH22
TIDR.7
TIDR.0
CH6
TIDR5
CH13
CH21
CH5
NAME AND DESCRIPTION
NAME AND DESCRIPTION
Transmit Idle Code Insertion Control Bits.
0 = do not insert the Idle Code in the TIDR into this channel
1 = insert the Idle Code in the TIDR into this channel
MSB of the Idle Code (this bit is transmitted first)
LSB of the Idle Code (this bit is transmitted last)
TIDR4
CH12
CH20
CH4
58 of 114
TIDR3
CH11
CH19
CH3
TIDR2
CH10
CH18
CH2
(LSB)
CH17
CH1
CH9
TIDR1
TIR2 (3D)
TIR1 (3C)
TIR3 (3E)
TIDR0
(LSB)