UPD720102GC-YEB-A Renesas Electronics America, UPD720102GC-YEB-A Datasheet - Page 25

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UPD720102GC-YEB-A

Manufacturer Part Number
UPD720102GC-YEB-A
Description
IC HOST CTLR USB2.0 3-PORTS QFP
Manufacturer
Renesas Electronics America

Specifications of UPD720102GC-YEB-A

Controller Type
USB 2.0 Controller
Interface
PCI
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
-20°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
120-TQFP
Package Type
TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Current - Supply
-
Lead Free Status / RoHS Status
Compliant, Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD720102GC-YEB-A
Manufacturer:
MICREL
Quantity:
11 560
Part Number:
UPD720102GC-YEB-A
Manufacturer:
RENESAS
Quantity:
664
Part Number:
UPD720102GC-YEB-A
Manufacturer:
NEC
Quantity:
12
Part Number:
UPD720102GC-YEB-A
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
UPD720102GC-YEB-A
Manufacturer:
RENESAS
Quantity:
8 000
Part Number:
UPD720102GC-YEB-A
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
Company:
Part Number:
UPD720102GC-YEB-A
Quantity:
4 200
Company:
Part Number:
UPD720102GC-YEB-A
Quantity:
312
Company:
Part Number:
UPD720102GC-YEB-A
Quantity:
308
Part Number:
UPD720102GC-YEB-A/JC
Manufacturer:
NEC
Quantity:
1 000
Part Number:
UPD720102GC-YEB-A/JC
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
USB interface block
Low-speed Source Electrical Characteristics
Rise time (10 to 90%)
Fall time (90 to 10%)
Differential rise and fall time matching
Low-speed data rate
Source jitter total (including frequency
tolerance):
Source jitter for differential transition to
SE0 transition
Receiver jitter:
Source SE0 interval of EOP
Receiver SE0 interval of EOP
Width of SE0 interval during differential
transition
Full-speed Source Electrical Characteristics
Rise time (10 to 90%)
Fall time (90 to 10%)
Differential rise and fall time matching
Full-speed data rate
Frame interval
Consecutive frame interval jitter
Source jitter total (including frequency
tolerance):
Source jitter for differential transition to
SE0 transition
Receiver jitter:
Source SE0 interval of EOP
Receiver SE0 interval of EOP
Width of SE0 interval during differential
transition
To next transition
For paired transitions
To next transition
For paired transitions
To next transition
For paired transitions
To next transition
For paired transitions
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
LR
LF
LRFM
LDRATHS
DDJ1
DDJ2
LDEOP
UJR1
UJR2
LEOPT
LEOPR
FST
FR
FF
FRFM
FDRATHS
FRAME
RFI
DJ1
DJ2
FDEOP
JR1
JR2
FEOPT
FEOPR
FST
Symbol
Data Sheet S17998EJ4V0DS
C
R
C
R
(t
Average bit rate
C
C
(t
Average bit rate
No clock adjustment
LR
FR
L
S
L
S
L
L
= 200 to 600 pF,
= 200 to 600 pF,
/t
= 50 pF
= 50 pF
= 36 Ω
= 36 Ω
/t
LF
FF
)
)
Conditions
1.49925
11.9940
0.9995
−18.5
−152
−200
Min.
1.25
−3.5
−4.0
−25
−14
−40
670
160
75
75
80
90
−2
−9
82
4
4
1.50075
12.0060
μ
111.11
1.0005
+18.5
Max.
+100
+152
+200
1.50
+3.5
+4.0
300
300
125
+25
+14
210
175
20
20
42
+5
+9
14
PD720102
Mbps
Mbps
Unit
ms
ns
ns
ns
ns
ns
ns
ns
μ
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
%
%
(1/2)
s
23

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