UPD720102GC-YEB-A Renesas Electronics America, UPD720102GC-YEB-A Datasheet

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The PD720102 complies with the universal serial bus specification revision 2.0 and open host controller interface specification for full-/low-speed signaling and Intel's enhanced host controller interface specification for high-speed signaling and works up to 480 Mbps. The 2.0 transceivers ...

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BLOCK DIAGRAM WakeUp_Event OHCI Host Controller PHY Port 1 2 PCI Bus INTA0 PCI Bus Interface Arbiter Root Hub Port 2 USB Bus Data Sheet S17998EJ4V0DS μ PD720102 PME0 WakeUp_Event EHCI Host Controller SMI0 Port 3 ...

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PCI Bus Interface : handles 32-bit 33 MHz PCI bus master and target function which comply with PCI specification revision 2.2. The number of enabled ports is set by bit in configuration space. Arbiter : arbitrates among two OHCI host ...

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PIN CONFIGURATION • 120-pin plastic TQFP (fine pitch) (14 × 14) μ PD720102GC-YEB-A PPON1 1 OCI20 V SS PPON2 OCI30 5 PPON3 V DD VCCRST0 PME0 10 N.C. PCLK V SS VBBRST0 INTA0 15 GNT0 REQ0 AD31 V DD AD30 ...

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Pin Name • 120-pin plastic TQFP (fine pitch) (14 × 14) μ PD720102GC-YEB-A Pin No. Pin Name Pin No. 1 PPON1 31 2 OCI20 PPON2 34 5 OCI30 35 6 PPON3 ...

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PIN CONFIGURATION • 121-pin plastic FBGA (8 × 8) μ PD720102F1-CA7 ...

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Pin name • 121-pin plastic FBGA (8 × 8) μ PD720102F1-CA7-A Pin No. Pin Name 1 DP3 2 PPON1 3 OCI30 4 VCCRST0 5 PCLK 6 GNT0 7 AD30 8 AD28 9 AD25 10 CBE30 ...

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PIN INFORMATION Pin Name I/O Normal (Test) AD (31:0) I/O 3.3 V PCI I/O with OR input CBE (3:0)0 I/O 3.3 V PCI I/O with OR input PAR I/O 3.3 V PCI I/O with OR input FRAME0 I/O 3.3 ...

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Pin Name I/O Normal (Test) OCI (3:1)0 I (I/O) 3.3 V I/O buffer with OR input PPON (3:1) O (I/O) 3.3 V I/O buffer USB high speed D+ I/O DP (3:1) I/O DM (3:1) I/O USB high speed D− I/O ...

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HOW TO CONNECT TO EXTERNAL ELEMENTS 2.1 Handling Unused Pins To realize less than 3 ports host controller implementation, appropriate value shall be set to Port No field in EXT1 register. And unused pins shall be connected as shown ...

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Internal Regulator Circuit Connection Caution VDD15OUT must be routed to only V power supply of other ICs, this may cause unstable operation of the Remark V is powered by VDD15OUT from internal regulator not necessary to use ...

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Crystal Connection μ The following crystals are evaluated on our reference design board. Table 2-2 shows the external parameters. Vender Note 1 KDS AT-49 30.000 MHz Note 2 NDK AT-41 30.000 MHz Notes 1. DAISHINKU CORP. 2. NIHON DEMPA ...

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External Serial ROM Connection Figure 2–5. External Serial ROM Connection μ The following serial ROM is used on our reference design board. Vender Atmel Corporation SRMOD/SRCLK/SRDTA can be opened, when serial ROM is not necessary on board. 3.3 V ...

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ELECTRICAL SPECIFICATIONS 3.1 Buffer List • 3.3 V input buffer CLKSEL, HSMODE • 3.3 V input buffer with pull down resistor SRMOD, TESTEN, TEST3, TEST4 • 3.3 V input schmitt buffer VBBRST0, VCCRST0 • 3 ...

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Terminology Terms Used in Absolute Maximum Ratings Parameter Symbol Power supply voltage DD15, AV DD33 AV DD15 Input voltage V I Output voltage V O Output current I O Operating ambient temperature T A Storage ...

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Terms Used in DC Characteristics Parameter Symbol Off-state output leakage current I OZ Input leakage current I I Low-level output current I OL High-level output current Meaning Indicates the current that flows from the power supply pins ...

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Electrical Specifications Absolute Maximum Ratings Parameter Symbol Power supply voltage DD15 Input voltage, 3.3 V buffer V I Output voltage, 3.3 V buffer V O Output current I O Operating ambient temperature T A ...

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DC Characteristics (V = 3.135 to 3.465 Control pin block Parameter Off-state output current Low-level output current 3.3 V low-level output current (9 mA) High-level output current 3.3 V high-level output current (9 mA) Input leakage current ...

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USB interface block Parameter Output pin impedance Input Levels for Low-/full-speed: High-level input voltage (drive) High-level input voltage (floating) Low-level input voltage Differential input sensitivity Differential common mode range Output Levels for Low-/full-speed: High-level output voltage Low-level output voltage SE1 ...

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Figure 3–1. Differential Input Sensitivity Range for Low-/full-speed −1.0 0.0 0.2 0.4 0.6 0.8 Figure 3–2. Receiver Sensitivity for Transceiver at DP/DM Level 1 Level 2 0% Figure 3–3. Receiver Measurement Fixtures USB Vbus Connector D+ Nearest D− Device Gnd ...

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Power consumption Parameter Symbol Power P Device state = D0, All the ports does not connect to any WD0-0 Consumption function, and each OHCI controller is under USB suspend and EHCI controller is stopped. P The power consumption under the ...

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AC Characteristics (V = 3.135 to 3.465 System clock ratings Parameter Clock frequency Clock duty cycle Remarks 1. Recommended accuracy of clock frequency is ± 100 ppm. 2. Required accuracy of crystal or oscillator block is including ...

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USB interface block Parameter Low-speed Source Electrical Characteristics Rise time (10 to 90%) Fall time (90 to 10%) Differential rise and fall time matching Low-speed data rate Source jitter total (including frequency tolerance): To next transition For paired transitions Source ...

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Parameter High-speed Source Electrical Characteristics Rise time (10 to 90%) Fall time (90 to 10%) Driver waveform High-speed data rate Microframe interval Consecutive microframe interval difference Data source jitter Receiver jitter tolerance Hub Event Timings Time to detect a downstream ...

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Figure 3–4. Transmit Waveform for Transceiver at DP/DM Level 1 Point 3 Point 1 Point 5 Level 2 Unit Interval 0% Figure 3–5. Transmitter Measurement Fixtures Test Supply Voltage 15.8 Ω USB Vbus Connector D+ Nearest D− 15.8 Ω Device ...

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Timing Diagram PCI clock 0.6V DD 0.5V DD 0.4V DD 0.3V DD 0.2V DD PCI reset PCLK PWR_GOOD VBBRST0 PCI Signals 26 t cyc t t high low 100 ms (Typ.) t rst-clk t rst Data Sheet S17998EJ4V0DS μ ...

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PCI output timing measurement condition PCLK Output delay 3-state output delay PCI input timing measurement condition PCLK Input 0. (ptp) val val 0.615V (for falling edge) DD 0.285V (for falling edge) DD ...

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USB differential data jitter for full-speed t PERIOD Differential Data Lines N × t USB differential-to-EOP transition skew and EOP width for low-/full-speed t PERIOD Crossover Point Differential Data Lines Diff. Data-to- SE0 Skew N × t USB receiver jitter ...

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Low-/full-speed disconnect detection D+/D− V (Min.) IZH V IL D−/ Device Disconnected Full-/high-speed device connect detection Device Connected Low-speed device connect detection Device Connected t DDIS Disconnect Detected D+ D− ...

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PACKAGE DRAWINGS μ • PD720102GC-YEB-A 120-PIN PLASTIC TQFP (FINE PITCH) (14x14 120 NOTE Each lead centerline is located within 0. its true position (T.P.) at maximum material condition. ...

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PD720102F1-CA7-A 121-PIN PLASTIC FBGA (8x8) D INDEX MARK φ φ Data Sheet S17998EJ4V0DS ...

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RECOMMENDED SOLDERING CONDITIONS μ The PD720102 should be soldered and mounted under the following recommended conditions. For soldering methods and conditions other than those recommended below, contact an NEC Electronics sales representative. For technical information, see the following website. ...

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Data Sheet S17998EJ4V0DS μ PD720102 33 ...

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Data Sheet S17998EJ4V0DS μ PD720102 ...

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NOTES FOR CMOS DEVICES 1 VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between V malfunction. Take care ...

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USB logo is a trademark of USB Implementers Forum, Inc. Windows is either a registered trademark or a trademark of Microsoft Corporation in the United States and/or other countries. • The information in this document is current as of March, ...