LAN9221-ABZJ SMSC, LAN9221-ABZJ Datasheet - Page 21

• Manufacturer Part Number: LAN9221-ABZJ
• Description: IC ETHERNET CTRLR 16BIT 56-QFN
• Manufacturer: SMSC
• Type: Single Chip MAC and PHY Controllerr

Specifications of LAN9221-ABZJ

• Controller Type: Ethernet Controller, MAC/PHY
• Interface: Serial EEPROM
• Voltage - Supply: 3.3V
• Current - Supply: 85mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-QFN
• Product: Ethernet Controllers
• Number Of Transceivers: 1
• Standard Supported: IEEE 802.3 or IEEE 802.3u
• Data Rate: 10 Mbps or 100 Mbps
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 0 V
• Supply Current (max): 99.2 mA, 137.3 mA
• Maximum Operating Temperature: + 70 C
• Ethernet Connection Type: 10BASE-T or 100BASE-TX
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• No. Of Ports: 2
• Ethernet Type: IEEE 802.3 / 802.3u
• Interface Type: HBI
• Supply Current: 85mA
• Supply Voltage Range: 1.62V To 3.6V
• Operating Temperature Range: 0°C To +70°C
• Rohs Compliant: Yes
• For Use With: 638-1074 - EVALUATION BOARD LAN9221-ABZJ
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 638-1073

USB 2.0 to 10/100 Ethernet Controller
Datasheet
SMSC LAN950x Family
(Figure
NUM PINS
NUM PINS
NUM PINS
Exposed
package
pad on
bottom
1
4
1
1
5
2
1
3.1)
Power Supply
Power Supply
Power Supply
PHY Interrupt
PHY Interrupt
+3.3V Analog
(Internal PHY
External PHY
Bias Resistor
Ethernet PLL
No Connect
PHY Mode)
Digital Core
+3.3V I/O
(External
Ground
Output
NAME
NAME
NAME
Mode)
Power
Table 3.7 I/O Power Pins, Core Power Pins, and Ground Pad
VDDCORE
nPHY_INT
nPHY_INT
SYMBOL
SYMBOL
VDD33IO
SYMBOL
Table 3.6 Ethernet PHY Pins (continued)
VDD33A
VDDPLL
EXRES
VSS
NC
Table 3.8 No-Connect Pins
DATASHEET
BUFFER
BUFFER
BUFFER
TYPE
TYPE
TYPE
(PU)
O8
IS
AI
P
P
P
P
P
21
-
In internal PHY mode, this pin can be configured
to output the internal PHY interrupt signal.
Note:
In external PHY mode, the active-low signal on
this pin is input from the external PHY and
indicates a PHY interrupt has occurred.
Refer to the device reference schematic for
connection information.
Note:
external resistor to ground.
This pin must be connected to VDDCORE for
proper operation.
Refer to
page 24
additional connection information.
Refer to the device reference schematic for
connection information.
Refer to
page 24
connection information.
Common Ground
These pins must be left floating for normal device
operation.
Used for the internal bias circuits. Connect to an
For LAN9500A/LAN9500Ai use 12.0K, 1%.
For LAN9500/LAN9500i use 12.4K, 1%.
and the device reference schematic for
and the device reference schematic for
Chapter 4, "Power Connections," on
Chapter 4, "Power Connections," on
The internal PHY interrupt signal is
active-high.
Pin 7 is a no-connect (NC) for
LAN9500A/LAN9500Ai, but may be
connected to VDD33A for backward
compatibility with LAN9500/LAN9500i.
DESCRIPTION
DESCRIPTION
DESCRIPTION
Revision 1.0 (05-17-10)