LAN9221-ABZJ SMSC, LAN9221-ABZJ Datasheet - Page 17

• Manufacturer Part Number: LAN9221-ABZJ
• Description: IC ETHERNET CTRLR 16BIT 56-QFN
• Manufacturer: SMSC
• Type: Single Chip MAC and PHY Controllerr

Specifications of LAN9221-ABZJ

• Controller Type: Ethernet Controller, MAC/PHY
• Interface: Serial EEPROM
• Voltage - Supply: 3.3V
• Current - Supply: 85mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-QFN
• Product: Ethernet Controllers
• Number Of Transceivers: 1
• Standard Supported: IEEE 802.3 or IEEE 802.3u
• Data Rate: 10 Mbps or 100 Mbps
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 0 V
• Supply Current (max): 99.2 mA, 137.3 mA
• Maximum Operating Temperature: + 70 C
• Ethernet Connection Type: 10BASE-T or 100BASE-TX
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• No. Of Ports: 2
• Ethernet Type: IEEE 802.3 / 802.3u
• Interface Type: HBI
• Supply Current: 85mA
• Supply Voltage Range: 1.62V To 3.6V
• Operating Temperature Range: 0°C To +70°C
• Rohs Compliant: Yes
• For Use With: 638-1074 - EVALUATION BOARD LAN9221-ABZJ
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 638-1073

USB 2.0 to 10/100 Ethernet Controller
Datasheet
SMSC LAN950x Family
NUM PINS
1
1
1
1
1
(Internal PHY
Receive Data
(Internal PHY
(Internal PHY
Receive Data
(Internal PHY
Receive Data
(Internal PHY
Receive Data
Mode Select
PHY Mode)
PHY Mode)
PHY Mode)
PHY Mode)
PHY Mode)
PHY Reset
Port Reset
JTAG Test
JTAG Test
JTAG Test
JTAG Test
JTAG Test
Data Input
Data Out
(External
(External
(External
(External
(External
NAME
Mode)
Mode)
Mode)
Mode)
Mode)
Clock
0
1
2
3
nPHY_RST
SYMBOL
nTRST
RXD0
RXD1
RXD2
RXD3
TDO
TCK
TMS
TDI
Table 3.3 JTAG Pins
DATASHEET
BUFFER
TYPE
(PU)
(PD)
(PU)
(PD)
(PU)
(PD)
(PU)
(PD)
O8
O8
IS
IS
IS
IS
IS
IS
IS
IS
17
In internal PHY mode, this active-low pin
functions as the JTAG test port reset input.
In external PHY mode, this pin functions as the
receive data 0 input from the external PHY.
In internal PHY mode, this pin functions as the
JTAG data output.
In external PHY mode, this active-low pin
functions as the PHY reset output.
In internal PHY mode, this pin functions as the
JTAG test clock. The maximum operating
frequency of this clock is 25MHz.
In external PHY mode, this pin functions as the
receive data 1 input from the external PHY.
In internal PHY mode, this pin functions as the
JTAG test mode select.
In external PHY mode, this pin functions as the
receive data 2 input from the external PHY.
In internal PHY mode, this pin functions as the
JTAG data input.
In external PHY mode, this pin functions as the
receive data 3 input from the external PHY.
DESCRIPTION
Revision 1.0 (05-17-10)