CS42324-CQZ Cirrus Logic Inc, CS42324-CQZ Datasheet - Page 4

• Manufacturer Part Number: CS42324-CQZ
• Description: IC CODEC STEREO AUDIO 48LQFP
• Manufacturer: Cirrus Logic Inc
• Type: Audio Codecr

Specifications of CS42324-CQZ

• Package / Case: 48-LQFP
• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 1 / 2
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 95 / 100
• Voltage - Supply, Analog: 3.13 V ~ 3.47 V
• Voltage - Supply, Digital: 3.13 V ~ 3.47 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Number Of Adc Inputs: 1
• Number Of Dac Outputs: 2
• Conversion Rate: 96 KSPS
• Interface Type: Serial (I2S, SPI)
• Resolution: 24 bit
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Number Of Channels: 1 ADC/2 DAC
• Supply Current: 10 mA to 24 mA
• Thd Plus Noise: - 88 dB ADC / - 90 dB DAC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1498 - BOARD EVAL FOR CS42324 CODEC
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1602

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5. REGISTER QUICK REFERENCE ........................................................................................................ 44
6. REGISTER DESCRIPTION .................................................................................................................. 46
4.7 Interrupts and Overflow .................................................................................................................. 43
6.1 Device I.D. and Revision Register (Address 00h) (Read Only) ...................................................... 46
6.2 Mute Control (Address 01h) ........................................................................................................... 46
6.3 Operational Control (Address 02h) ................................................................................................. 47
6.4 Serial Port 1 Control (Address 03h) ................................................................................................ 49
6.5 Serial Port 2 Control (Address 04h) ................................................................................................ 50
6.6 ADC Clocking (Address 06h) .......................................................................................................... 50
6.7 DAC1 Clocking (Address 07h) ........................................................................................................ 51
6.8 DAC2 Clocking (Address 08h) ........................................................................................................ 52
6.9 ADC Control (Address 0Ah) ........................................................................................................... 52
6.10 DAC1 Control (Address 0Bh) ....................................................................................................... 53
4.6.1 Hardware Mode ..................................................................................................................... 40
4.6.2 Software Mode - I²C Control Port .......................................................................................... 41
4.6.3 Software Mode - SPI Control Port ......................................................................................... 42
4.6.4 Memory Address Pointer (MAP) ............................................................................................ 43
6.1.1 Device I.D. (Read Only) ........................................................................................................ 46
6.1.2 Chip Revision (Read Only) .................................................................................................... 46
6.2.1 System MCLK Source ........................................................................................................... 46
6.2.2 Mute DAC2 Left-Channel ...................................................................................................... 46
6.2.3 Mute DAC2 Right-Channel .................................................................................................... 47
6.2.4 Mute DAC1 Left-Channel ...................................................................................................... 47
6.2.5 Mute DAC1 Right-Channel .................................................................................................... 47
6.2.6 Mute ADC Left-Channel ........................................................................................................ 47
6.2.7 Mute ADC Right-Channel ...................................................................................................... 47
6.3.1 Global Power-Down .............................................................................................................. 47
6.3.2 INT Pin High/Low Active (INT_H/L) ....................................................................................... 48
6.3.3 Freeze ................................................................................................................................... 48
6.3.4 Tri-State SDOUT ................................................................................................................... 48
6.3.5 Tri-State Serial Port 1 ............................................................................................................ 48
6.3.6 Tri-State Serial Port 2 ............................................................................................................ 49
6.4.1 Serial Port 1 Master/Slave Select .......................................................................................... 49
6.4.2 Serial Port 1 Speed Mode ..................................................................................................... 49
6.4.3 MCLK1 Divider ...................................................................................................................... 49
6.4.4 Serial Port 1 MCLK source .................................................................................................... 49
6.5.1 Serial Port 2 Master/Slave Select .......................................................................................... 50
6.5.2 Serial Port 2 Speed Mode ..................................................................................................... 50
6.5.3 MCLK2 Divider ...................................................................................................................... 50
6.5.4 Serial Port 2 MCLK Source ................................................................................................... 50
6.6.1 ADC MCLK Source ............................................................................................................... 50
6.6.2 ADC Serial Port Source ......................................................................................................... 51
6.6.3 ADC Digital Interface Format (ADC_DIF) .............................................................................. 51
6.7.1 DAC1 MCLK Source ............................................................................................................. 51
6.7.2 DAC1 Serial Port Source ....................................................................................................... 51
6.7.3 DAC1 Digital Interface Format (DAC1_DIF) .......................................................................... 51
6.8.1 DAC2 MCLK Source ............................................................................................................. 52
6.8.2 DAC2 Serial Port Source ....................................................................................................... 52
6.8.3 DAC2 Digital Interface Format (DAC2_DIF) .......................................................................... 52
6.9.1 ADC High-Pass Filter Freeze ................................................................................................ 52
6.9.2 ADC Soft Ramp Control ........................................................................................................ 52
6.9.3 Analog Input Selection .......................................................................................................... 53
6.10.1 DAC1 De-Emphasis Control ................................................................................................ 53
6.10.2 DAC1 Single Volume Control .............................................................................................. 53
CS42324
DS721A6