CS42324-CQZ Cirrus Logic Inc, CS42324-CQZ Datasheet - Page 35

• Manufacturer Part Number: CS42324-CQZ
• Description: IC CODEC STEREO AUDIO 48LQFP
• Manufacturer: Cirrus Logic Inc
• Type: Audio Codecr

Specifications of CS42324-CQZ

• Package / Case: 48-LQFP
• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 1 / 2
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 95 / 100
• Voltage - Supply, Analog: 3.13 V ~ 3.47 V
• Voltage - Supply, Digital: 3.13 V ~ 3.47 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Number Of Adc Inputs: 1
• Number Of Dac Outputs: 2
• Conversion Rate: 96 KSPS
• Interface Type: Serial (I2S, SPI)
• Resolution: 24 bit
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Number Of Channels: 1 ADC/2 DAC
• Supply Current: 10 mA to 24 mA
• Thd Plus Noise: - 88 dB ADC / - 90 dB DAC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1498 - BOARD EVAL FOR CS42324 CODEC
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1602

DS721A6
4.4.3
4.4.4
4.4.5
De-Emphasis Filter
The CS42324 includes on-chip digital de-emphasis optimized for a sample rate of 44.1 kHz. The filter re-
sponse is shown in
with changes in sample rate, Fs.
The de-emphasis feature is included to accommodate audio recordings that utilize 50/15 μs pre-emphasis
equalization as a means of noise reduction. De-emphasis is only available in Single-Speed Mode
Internal Digital Loopback
The CS42324 supports an internal digital loopback mode in which the ADC’s output data can be internally
routed to either of the DAC inputs. This mode may be activated by setting the DACx_LOOP_BACK bit in
“DAC1 Control (Address 0Bh)” on page 53
mode, the ADC and DAC will need to operate at the same synchronous sample rate. When the
DACx_LOOP_BACK bit is set, the respective DACx_DIF[2:0] bits must be set to the same value as the
ADC_DIF[2:0] register.
During loop back mode, the ADC data will continue to be present on the SDOUT pin in the format selected
by the ADC_DIF[2:0] bits.
DAC Description
The CS42324 uses a switched current architecture followed by on chip current to voltage conversion and
continuous time low-pass filter. The digital interpolator response is shown in the
sponse Plots” on page
tion Diagrams” on page
The CS42324 DAC does not include phase or amplitude compensation for an external filter. Therefore,
the DAC system phase and amplitude response will be dependent on the external analog circuitry.
-10dB
Figure
Gain
0dB
dB
67. The recommended external analog circuitry is shown in the
26.
17. The frequency response of the de-emphasis curve will scale proportionally
Figure 17. De-Emphasis Curve
3.183 kHz
T1=50 µs
F1
and
“DAC2 Control (Address 0Ch)” on page
10.61 kHz
F2
T2 = 15 µs
Frequency
“DAC Digital Filter Re-
“Typical Connec-
55. During this
CS42324
35