CS4270-DZZ Cirrus Logic Inc, CS4270-DZZ Datasheet - Page 31

• Manufacturer Part Number: CS4270-DZZ
• Description: IC CODEC 24BIT 105DB 24TSSOP
• Manufacturer: Cirrus Logic Inc
• Type: Stereo Audior

Specifications of CS4270-DZZ

• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 105 / 105
• Voltage - Supply, Analog: 3.1 V ~ 5.25 V
• Voltage - Supply, Digital: 3.1 V ~ 5.25 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-TSSOP
• Audio Codec Type: Stereo
• No. Of Adcs: 1
• No. Of Dacs: 1
• No. Of Input Channels: 3
• No. Of Output Channels: 3
• Adc / Dac Resolution: 24bit
• Sampling Rate: 216kSPS
• Ic Interface Type: I2C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1002 - BOARD EVAL FOR CS4270 CODEC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 598-1622

DS686F1
6.2.3
7. REGISTER QUICK REFERENCE
This table shows the register and register bit names and their associated default values.
Addr
01h Device ID
p 32
02h Power Control
p 32
03h Mode Control
p 33
04h ADC and DAC
p 34
05h Transition
p 35
06h Mute Control
p 36
07h DAC Channel A
p 36
08h DAC Channel B
p 37
Control
Control
Volume Control
Volume Control
Function
The device has MAP auto increment capability enabled by the INCR bit (the MSB) of the MAP. If INCR is
set to 0, MAP will stay constant for successive I²C writes or reads and SPI writes. If INCR is set to 1, MAP
will auto increment after each byte is written, allowing block reads or writes of successive registers.
Memory Address Pointer (MAP)
The MAP byte comes after the address byte and selects the register to be read or written. Refer to
Figures 20
6.2.3.1
DAC_SNGL_
and
ADC_HPF_
Map Increment (INCR)
Reserved
Reserved
DACA_
DACB_
FRZ_A
Freeze
VOL7
VOL7
VOL
ID3
21 on page
7
1
0
0
0
0
0
0
0
DAC_SOFT DAC_ZC
ADC_HPF_
Reserved PDN_ADC Reserved Reserved Reserved
Reserved
Reserved
DACA_
DACB_
FRZ_B
VOL6
VOL6
ID2
29, and
6
1
0
0
0
1
0
0
0
Figure 22 on page
LOOPBK
AUTO_
DACA_
DACB_
MUTE
VOL5
VOL5
DIG_
FM1
ID1
5
0
0
1
0
1
1
0
0
DAC_DIF1 DAC_DIF0 Reserved
ADC_INV_
ADC_CHB
MUTE_
DACA_
DACB_
VOL4
VOL4
FM0
ID0
B
4
0
0
1
0
0
0
0
0
30.
ADC_CH A
ADC_INV_
MCLK_
FREQ2
MUTE_
DACA_
DACB_
REV3
VOL3
VOL3
3
A
0
0
0
0
0
0
0
0
DAC_INV_
MCLK_
FREQ1
MUTE_
DACA_
DACB_
REV2
VOL2
VOL2
POL
2
B
0
0
0
0
0
0
0
0
MUTE_DAC_
DAC_INV_A
PDN_DAC
Reserved
MCLK_
FREQ0
DACA_
DACB_
REV1
VOL1
VOL1
CHB
1
0
0
0
0
0
0
0
0
MUTE_DAC_
CS4270
ADC_DIF0
DE_EMPH
DACA_
DACB_
POPG
REV0
VOL0
VOL0
PDN
CHA
0
1
0
0
0
0
0
0
0
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