CS42L51-CNZ Cirrus Logic Inc, CS42L51-CNZ Datasheet - Page 52

IC CODEC STEREO W/HDPN AMP 32QFN

CS42L51-CNZ

Manufacturer Part Number
CS42L51-CNZ
Description
IC CODEC STEREO W/HDPN AMP 32QFN
Manufacturer
Cirrus Logic Inc
Type
Stereo Audior
Datasheet

Specifications of CS42L51-CNZ

Package / Case
32-QFP
Data Interface
PCM Audio Interface
Resolution (bits)
24 b
Number Of Adcs / Dacs
2 / 2
Sigma Delta
Yes
Dynamic Range, Adcs / Dacs (db) Typ
98 / 98
Voltage - Supply, Analog
1.8V, 2.5V
Voltage - Supply, Digital
1.8V, 2.5V
Operating Temperature
-10°C ~ 70°C
Mounting Type
Surface Mount
Number Of Adc Inputs
6
Number Of Dac Outputs
2
Conversion Rate
96 KSPS
Interface Type
Serial (2-Wire, 3-Wire, I2C, SPI)
Resolution
24 bit
Operating Supply Voltage
1.8 V / 2.5 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 10 C
Number Of Channels
2 ADC/2 DAC
Thd Plus Noise
- 88 dB ADC / - 86 dB DAC
Peak Reflow Compatible (260 C)
No
Leaded Process Compatible
No
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
598-1005 - BOARD EVAL FOR CS42L51 CODEC
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
598-1045

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52
6.4
SDOUT->SDIN
7
Interface Control (Address 04h)
SDOUT to SDIN Loopback (SDOUT->SDIN)
Default: 0
0 - Disabled; SDOUT internally disconnected from SDIN
1 - Enabled; SDOUT internally connected to SDIN
Function:
Internally loops the signal on the SDOUT pin to SDIN.
Master/Slave Mode (M/S)
Default: 0
0 - Slave
1 - Master
Function:
Selects either master or slave operation for the serial port.
DAC Digital Interface Format (DAC_DIF[2:0])
Default = 000
Function:
Selects the digital interface format used for the data in on SDIN. The required relationship between the
Left/Right clock, serial clock and serial data is defined by the Digital Interface Format and the options are
detailed in the section
DAC_DIF[2:0]
000
001
010
100
101
100
011
110
M/S
6
Left-Justified, up to 24-bit data
I²S, up to 24-bit data
Right-Justified, 24-bit data
Right-Justified, 20-bit data
Right-Justified, 18-bit data
Right-Justified, 16-bit data
Reserved
Reserved
“Digital Interface Formats” on page
DAC_DIF2
5
Description
DAC_DIF1
4
DAC_DIF0
3
40.
ADC_I²S/LJ
2
20 on page 41
19 on page 40
21 on page 41
21 on page 41
21 on page 41
21 on page 41
Figure
-
-
DIGMIX
1
CS42L51
MICMIX
DS679F1
0

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