CS42L51-CNZ Cirrus Logic Inc, CS42L51-CNZ Datasheet - Page 44

• Manufacturer Part Number: CS42L51-CNZ
• Description: IC CODEC STEREO W/HDPN AMP 32QFN
• Manufacturer: Cirrus Logic Inc
• Type: Stereo Audior

Specifications of CS42L51-CNZ

• Package / Case: 32-QFP
• Data Interface: PCM Audio Interface
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 98 / 98
• Voltage - Supply, Analog: 1.8V, 2.5V
• Voltage - Supply, Digital: 1.8V, 2.5V
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Number Of Adc Inputs: 6
• Number Of Dac Outputs: 2
• Conversion Rate: 96 KSPS
• Interface Type: Serial (2-Wire, 3-Wire, I2C, SPI)
• Resolution: 24 bit
• Operating Supply Voltage: 1.8 V / 2.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 10 C
• Number Of Channels: 2 ADC/2 DAC
• Thd Plus Noise: - 88 dB ADC / - 86 dB DAC
• Peak Reflow Compatible (260 C): No
• Leaded Process Compatible: No
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1005 - BOARD EVAL FOR CS42L51 CODEC
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1045

44
SCL
SDA
SDA
SCL
START
the contents of the register pointed to by the MAP will be output. Setting the auto-increment bit in MAP
allows successive reads or writes of consecutive registers. Each byte is separated by an acknowledge
bit. The ACK bit is output from the
the microcontroller after each transmitted byte.
Since the read operation cannot set the MAP, an aborted write operation is used as a preamble. As shown
in
dition. The following pseudocode illustrates an aborted write operation followed by a read operation.
Setting the auto-increment bit in the MAP allows successive reads or writes of consecutive registers. Each
byte is separated by an acknowledge bit.
START
Figure
0
1
CHIP ADDRESS (WRITE)
0
1
1
0
CHIP ADDRESS (WRITE)
Send start condition.
Send 100101x0 (chip address & write operation).
Receive acknowledge bit.
Send MAP byte, auto-increment off.
Receive acknowledge bit.
Send stop condition, aborting write.
Send start condition.
Send 100101x1 (chip address & read operation).
Receive acknowledge bit.
Receive byte, contents of selected register.
Send acknowledge bit.
Send stop condition.
0
2
1
0
25, the write operation is aborted after the acknowledge for the MAP byte by sending a stop con-
1
3
0
2
0 1 AD0 0
4
1
3
5
0
4
6
1
5
7
AD0
ACK
6
8
7
9
INCR
0
ACK
10 11
Figure 25. Control Port Timing, I²C Read
Figure 24. Control Port Timing, I²C Write
8
6
INCR
9
5
MAP BYTE
12 13 14 15
10 11
4
6
CS42L51
MAP BYTE
3
5
2
12
4
1
13 14 15
3
16
0
ACK
after each input byte is read and is input to the
2
STOP
17 18
START
1
16 17 18
0
19
ACK
1
20 21 22 23 24
CHIP ADDRESS (READ)
0
7
0
19
6
DATA
1
0
24 25
1
1 AD0 1
0
25
ACK
26
26 27 28
27 28
ACK
7
DATA +1
6
7
DATA
0
1
ACK
0
DATA +1
7
7
DATA +n
0
6
DATA + n
1
7
CS42L51
CS42L51
0
0
ACK
ACK
NO
STOP
DS679F1
STOP
from