PLDC20G10-25PC Cypress Semiconductor Corp, PLDC20G10-25PC Datasheet - Page 2

• Manufacturer Part Number: PLDC20G10-25PC
• Description: IC SPLD 10MACROCELL 25NS 24-DIP
• Manufacturer: Cypress Semiconductor Corp

Specifications of PLDC20G10-25PC

• Programmable Type: SPLD
• Number Of Macrocells: 10
• Voltage - Input: 5V
• Speed: 25ns
• Mounting Type: Through Hole
• Package / Case: 24-DIP (0.300", 7.62mm)
• Family Name: PLDC20G10
• Process Technology: CMOS
• # Macrocells: 10
• # I/os (max): 10
• Propagation Delay Time: 25ns
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temp Range: 0C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 24
• Supply Current: 55mA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1284

Selection Guide
Functional Description
Cypress PLDC20G10 uses an advanced 0.8-micron CMOS
technology and a proven EPROM cell as the programmable
element. This technology and the inherent advantage of being
able to program and erase each cell enhances the reliability
and testability of the circuit. This reduces the burden on the
customer to test and to handle rejects.
A preload function allows the registered outputs to be preset
to any pattern during testing. Preload is important for testing
the functionality of the Cypress PLD device.
20G10 Functional Description
The PLDC20G10 is a generic 24-pin device that can be pro-
grammed to logic functions that include but are not limited to:
20L10, 20L8, 20R8, 20R6, 20R4, 12L10, 14L8, 16L6, 18L4,
20L2, and 20V8. Thus, the PLDC20G10 provides significant
design, inventory and programming flexibility over dedicated
24-pin devices. It is executed in a 24-pin 300-mil molded DIP
and a 300-mil windowed cerDIP. It provides up to 22 inputs and
10 outputs. When the windowed cerDIP is exposed to UV light,
the 20G10 is erased and then can be reprogrammed.
The programmable output cell provides the capability of defin-
ing the architecture of each output individually. Each of the 10
output cells may be configured with registered or combinatorial
outputs, active HIGH or active LOW outputs, and product term
or Pin 13 generated output enables. Three architecture bits
determine the configurations as shown in the Configuration
Document #: 38-03010 Rev. **
20G10B–15
20G10B–20
20G10B–25
20G10–25
20G10–30
20G10–35
20G10–40
Part Number
Generic
Com/Ind
70
70
55
55
I
CC
(continued)
(mA)
100
100
Mil
80
80
Com/Ind
15
20
25
35
t
PD
(ns)
Table and in Figures 1 through 8. A total of eight different con-
figurations are possible, with the two most common shown in
Figure 3 and Figure 5. The default or unprogrammed state is
registered/active/LOW/Pin 11 OE. The entire programmable
output cell is shown in the next section.
The architecture bit ‘C1’ controls the registered/combinatorial
option. In either combinatorial or registered configuration, the
output can serve as an I/O pin, or if the output is disabled, as
an input only. Any unused inputs should be tied to ground. In
either registered or combinatorial configuration, the output of
the register is fed back to the array. This allows the creation of
control-state machines by providing the next state. The regis-
ter is clocked by the signal from Pin 1. The register is initialized
on power up to Q output LOW and Q output HIGH.
In both the combinatorial and registered configurations, the
source of the output enable signal can be individually chosen
with architecture bit ‘C2’. The OE signal may be generated
within the array, or from the external OE (Pin 13). The Pin 13
allows direct control of the outputs, hence having faster en-
able/disable times.
Each output cell can be configured for output polarity. The out-
put can be either active HIGH or active LOW. This option is
controlled by architecture bit ‘C0’.
Along with this increase in functional density, the Cypress
PLDC20G10 provides lower-power operation through the use
of CMOS technology and increased testability with a register
preload feature.
Mil
20
25
30
40
Com/Ind
12
12
15
30
PLDC20G10B/PLDC20G10
t
S
(ns)
Mil
15
18
20
35
Com/Ind
10
12
15
25
t
CO
(ns)
Page 2 of 13
Mil
15
15
20
25