PLDC20G10-25PC Cypress Semiconductor Corp, PLDC20G10-25PC Datasheet

IC SPLD 10MACROCELL 25NS 24-DIP

PLDC20G10-25PC

Manufacturer Part Number
PLDC20G10-25PC
Description
IC SPLD 10MACROCELL 25NS 24-DIP
Manufacturer
Cypress Semiconductor Corp
Datasheets

Specifications of PLDC20G10-25PC

Programmable Type
SPLD
Number Of Macrocells
10
Voltage - Input
5V
Speed
25ns
Mounting Type
Through Hole
Package / Case
24-DIP (0.300", 7.62mm)
Family Name
PLDC20G10
Process Technology
CMOS
# Macrocells
10
# I/os (max)
10
Propagation Delay Time
25ns
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Operating Temp Range
0C to 75C
Operating Temperature Classification
Commercial
Mounting
Through Hole
Pin Count
24
Supply Current
55mA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
428-1284

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PLDC20G10-25PC
Manufacturer:
CYP
Quantity:
5 510
Part Number:
PLDC20G10-25PC
Manufacturer:
TOS
Quantity:
5 510
Cypress Semiconductor Corporation
Document #: 38-03010 Rev. **
Features
• Fast
• Low power
• Commercial and military temperature range
• User-programmable output cells
• Generic architecture to replace standard logic func-
• Eight product terms and one OE product term per out-
Note:
1.
tions including: 20L10, 20L8, 20R8, 20R6, 20R4, 12L10,
14L8, 16L6, 18L4, 20L2, and 20V8
put
— Commercial: t
— Military: t
— I
— I
— Selectable for registered or combinatorial operation
— Output polarity control
— Output enable source selectable from pin 13 or prod-
The CG7C323 is the PLDC20G10 packaged in the JEDEC-compatible 28-pin PLCC pinout. Pin function and pin order is identical for both PLCC pinouts.
The difference is in the location of the “no connect” or NC pins.
uct term
Logic Block Diagram
CC
CC
Pin Configurations
I/OE
V
13
12
SS
max.: 70 mA, commercial
max.: 100 mA, military
NC
I
I
I
I
I
I
PD
5
6
7
8
9
10
11
OUTPUT
I/O
11
14
I
12131415161718
= 20 ns, t
4 3 2
CELL
PLDC20G10B
8
9
PLDC20G10
PD
Top View
LCC
1
= 15 ns, t
282726
OUTPUT
I/O
15
10
CO
I
CELL
8
8
25
24
23
22
21
20
19
= 15 ns, t
20G10–2
CO
NC
I/O
I/O
I/O
I/O
I/O
I/O
4
5
2
3
6
7
= 10 ns, t
OUTPUT
I/O
16
9
I
CELL
8
7
S
= 15 ns
3901 North First Street
S
OUTPUT
I/O
17
8
I
CELL
= 12 ns
NC
NC
NC
8
6
I
I
I
I
5
6
7
8
9
10
11
121314 1516 1718
4 3 2
OUTPUT
7
I/O
PLDC20G10B
I
18
PLDC20G10
CELL
STD PLCC
8
5
PROGRAMMABLE
Top View
ANDARRAY
1
2827 26
Reprogrammable Logic Device
Functional Description
Cypress PLD devices are high-speed electrically programma-
ble logic devices. These devices utilize the sum-of-products
(AND-OR) structure providing users the ability to program cus-
tom logic functions for unique requirements.
In an unprogrammed state the AND gates are connected via
EPROM cells to both the true and complement of every input.
By selectively programming the EPROM cells, AND gates may
be connected to either the true or complement or disconnected
from both true and complement inputs.
OUTPUT
• CMOS EPROM technology for reprogrammability
• Highly reliable
I/O
19
6
I
CELL
25
24
23
22
21
20
19
— Uses proven EPROM technology
— Fully AC and DC tested
— Security feature prevents logic pattern duplication
— 10% power supply voltage and higher noise immu-
8
4
nity
I/O
I/O
I/O
I/O
I/O
I/O
NC
3
5
7
2
4
6
OUTPUT
20G10–4
I/O
5
San Jose
PLDC20G10B/PLDC20G10
I
20
CELL
8
3
CMOS Generic 24-Pin
OUTPUT
I/O
NC
21
4
I
CELL
I
I
I
I
I
I
2
8
5
6
7
8
9
10
11
121314 1516 1718
4 3 2
JEDEC PLCC
CA 95134
CG7C323B–A
CG7C323–A
OUTPUT
I/O
22
3
Top View
I
CELL
8
1
1
2827 26
Revised March 26, 1997
OUTPUT
I/O
25
24
23
22
21
20
19
23
2
I
CELL
[1]
8
0
I/O
I/O
I/O
NC
I/O
I/O
I/O
408-943-2600
2
3
4
5
6
7
20G10–1
20G10–3
CP/I
V
24
1
CC

Related parts for PLDC20G10-25PC

PLDC20G10-25PC Summary of contents

Page 1

... Note: 1. The CG7C323 is the PLDC20G10 packaged in the JEDEC-compatible 28-pin PLCC pinout. Pin function and pin order is identical for both PLCC pinouts. The difference is in the location of the “no connect” pins. Cypress Semiconductor Corporation Document #: 38-03010 Rev. ** Reprogrammable Logic Device • ...

Page 2

... Preload is important for testing the functionality of the Cypress PLD device. 20G10 Functional Description The PLDC20G10 is a generic 24-pin device that can be pro- grammed to logic functions that include but are not limited to: 20L10, 20L8, 20R8, 20R6, 20R4, 12L10, 14L8, 16L6, 18L4, 20L2, and 20V8 ...

Page 3

... BACK 1 MUX C 3 PIN Product Term OE/Registered/Active LOW 1 Product Term OE/Registered/Active HIGH 0 Product Term OE/Combinatorial/Active LOW 1 Product Term OE/Combinatorial/Active HIGH 0 Pin 13 OE/Registered/Active LOW 1 Pin 13 OE/Registered/Active HIGH 0 Pin 13 OE/Combinatorial/Active LOW 1 Pin 13 OE/Combinatorial/Active HIGH PLDC20G10B/PLDC20G10 OUTPUT ENABLE MUX C 2 20G10–5 Configuration Page ...

Page 4

... Note: 2. Bidirectional I/O configurations are possible only when the combinatorial output option is selected Document #: 38-03010 Rev Figure 2. Product Term OE/Active HIGH Figure 4. Pin 13 OE/Active HIGH [ Figure 6. Product Term OE/Active HIGH Figure 8. Pin 13 OE/Active HIGH PLDC20G10B/PLDC20G10 20G10– 20G10– 20G10– ...

Page 5

... Tested initially and after any design or process changes that may affect these parameters. Document #: 38-03010 Rev Programming Voltage PLDC20G10B and CG7C323B–A ............................... 13.0V PLDC20G10 and CG7C323–A.................................... 14.0V Latch-Up Current..................................................... >200 mA Static Discharge Voltage ............................................. >500V (per MIL-STD-883, Method 8015) ...

Page 6

... B–15 B–20 Min. Max. Min. Max. Min. Max. Min. Max 45.4 41 and t . Part ( Test Loads and Waveforms used for t ER PZX PXZ + PLDC20G10B/PLDC20G10 R2 170 5 pF (236 MIL) 20G10–14 (b) 136 2.13V=V thm 20G10–16 Commercial –25 –35 Unit ...

Page 7

... WL [11] f Maximum Frequency MAX Switching Waveform INPUTS I/O, REGISTERED FEEDBACK REGISTERED OUTPUTS COMBINATORIAL OUTPUTS Document #: 38-03010 Rev (continued) B–20 Min. Max. Min. Max. Min. Max. Min. Max 33 PXZ PLDC20G10B/PLDC20G10 Military/Industrial B–25 –30 – 30.3 25.0 16.6 t PZX t ER Page Unit ns ns ...

Page 8

... OE 0 • • • • • • • • • • • • Document #: 38-03010 Rev PLDC20G10B/PLDC20G10 OUTPUT CELL 23 OUTPUT CELL 22 OUTPUT CELL 21 OUTPUT CELL 20 OUTPUT CELL 19 OUTPUT CELL 18 OUTPUT CELL 17 OUTPUT CELL 16 OUTPUT CELL 15 OUTPUT CELL 14 13 Page ...

Page 9

... (ns) (ns) (ns) (mA) Ordering Code PLDC20G10B–15PC PLDC20G10B–15WC 100 PLDC20G10B–20DMB PLDC20G10–25JC PLDC20G10–25PC/PI PLDC20G10–25WC PLDC20G10–30DMB PLDC20G10–30LMB PLDC20G10–30WMB PLDC20G10–35JC PLDC20G10–35PC MILITARY SPECIFICATIONS Group A Subgroup Testing DC Characteristics Parameter Subgroups Document #: 38-03010 Rev. ** PLDC20G10B/PLDC20G10 Package Name ...

Page 10

... Package Diagrams 24-Lead (300-Mil) CerDIP D14 MIL–STD–1835 D– 9Config.A 28-Square Leadless Chip Carrier L64 MIL–STD–1835 C–4 Document #: 38-03010 Rev. ** PLDC20G10B/PLDC20G10 28-Lead Plastic Leaded Chip Carrier J64 Page ...

Page 11

... Package Diagrams (continued) Document #: 38-03010 Rev. ** 28-Pin Windowed Leaded Chip Carrier H64 PLDC20G10B/PLDC20G10 Page ...

Page 12

... Package Diagrams (continued) Document #: 38-03010 Rev. ** 24-Lead (300-Mil) Molded DIP P13/P13A 24-Lead (300-Mil) Windowed CerDIP W14 MIL–STD–1835 D– 9Config.A PLDC20G10B/PLDC20G10 Page ...

Page 13

... Document Title: PLDC20G10B/PLDC20G10 CMOS Generic 24-Pin Reprogrammable Logic Device Document Number: 38-03010 REV. ECN NO. Issue Date ** 106292 04/25/01 Document #: 38-03010 Rev. ** © Cypress Semiconductor Corporation, 1997. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product ...

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