MC68MH360ZP33L Freescale Semiconductor, MC68MH360ZP33L Datasheet - Page 719

IC MPU 32BIT QUICC 357-PBGA

MC68MH360ZP33L

Manufacturer Part Number
MC68MH360ZP33L
Description
IC MPU 32BIT QUICC 357-PBGA
Manufacturer
Freescale Semiconductor
Datasheets

Specifications of MC68MH360ZP33L

Processor Type
M683xx 32-Bit
Speed
33MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
357-PBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC68MH360ZP33L
Manufacturer:
FREESCALE
Quantity:
1 831
Part Number:
MC68MH360ZP33L
Manufacturer:
MOTOLOLA
Quantity:
672
Part Number:
MC68MH360ZP33L
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC68MH360ZP33L
Manufacturer:
FREESCALE
Quantity:
20 000
Part Number:
MC68MH360ZP33LR2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
8.4.3 BYPASS
The BYPASS instruction selects the single-bit bypass register as shown in Figure 8-8. This
creates a shift register path from TDI to the bypass register and, finally, to TDO, circumvent-
ing the 196-bit boundary scan register. This instruction is used to enhance test efficiency
when a component other than the QUICC becomes the device under test.
When the bypass register is selected by the current instruction, the shift register stage is set
to a logic zero on the rising edge of TCK in the capture-DR controller state. Therefore, the
first bit to be shifted out after selecting the bypass register will always be a logic zero.
8.4.4 CLAMP
The CLAMP instruction selects the single-bit bypass register as shown in Figure 8-8, and
the state of all signals driven from system output pins is completely defined by the data pre-
viously shifted into the boundary scan register (for example, using the SAMPLE/PRELOAD
instruction).
8.4.5 HI-Z
The HI-Z instruction is provided as a manufacturer’s optional public instruction to prevent
having to backdrive the output pins during circuit-board testing. When HI-Z is invoked, all
output drivers, including the two-state drivers, are turned off (i.e., high impedance). The
instruction selects the bypass register.
8.5 QUICC RESTRICTIONS
The control afforded by the output enable signals using the boundary scan register and the
EXTEST instruction requires a compatible circuit-board test environment to avoid device-
MOTOROLA
provide some form of external synchronization to achieve mean-
ingful results.
Note that in the QUICC, the SAMPLE instruction is not function-
al.
On the QUICC, the TRIS pin may also be used during system re-
set to perform the same function.
FROM TDI
SHIFT DR
Freescale Semiconductor, Inc.
For More Information On This Product,
0
Figure 8-8. Bypass Register
MC68360 USER’S MANUAL
Go to: www.freescale.com
G1
1
1
Mux
NOTE
D
C
TO TDO
Scan Chain Test Access Port
8-11

Related parts for MC68MH360ZP33L