MPC8347EVVALFB Freescale Semiconductor, MPC8347EVVALFB Datasheet - Page 81

• Manufacturer Part Number: MPC8347EVVALFB
• Description: IC MPU POWERQUICC II 672-TBGA
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC II PROr

Specifications of MPC8347EVVALFB

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 667MHz
• Voltage: 1.3V
• Mounting Type: Surface Mount
• Package / Case: 672-TBGA
• Processor Series: MPC8xxx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: MPC8349E-MITXE
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• I/o Voltage: 1.8 V, 2.5 V, 3.3 V
• Minimum Operating Temperature: 0 C
• Core Size: 32 Bit
• Program Memory Size: 64KB
• Cpu Speed: 667MHz
• Embedded Interface Type: I2C, SPI, USB, UART
• Digital Ic Case Style: TBGA
• No. Of Pins: 672
• Rohs Compliant: Yes
• Family Name: MPC83xx
• Device Core: PowerQUICC II Pro
• Device Core Size: 32b
• Frequency (max): 667MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.3V
• Operating Supply Voltage (max): 1.36V
• Operating Supply Voltage (min): 1.24V
• Operating Temp Range: 0C to 105C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 672
• Package Type: TBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

19.2
RCWL[COREPLL] selects the ratio between the internal coherent system bus clock (csb_clk) and the e300
core clock (core_clk).
not listed in
Freescale Semiconductor
2
1
Core PLL Configuration
CFG_CLKIN_DIV
CFG_CLKIN_DIV doubles csb_clk if set high.
CLKIN is the input clock in host mode; PCI_CLK is the input clock in agent mode.
DDR2 memory may be used at 133 MHz provided that the memory components are specified for
operation at this frequency.
MPC8347E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 11
Table 59
at Reset
High
High
High
High
High
High
High
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
1
should be considered as reserved.
Table 59
Table 58. CSB Frequency Options for Agent Mode
shows the encodings for RCWL[COREPLL]. COREPLL values that are
SPMF
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0000
0010
0011
0100
0101
0110
0111
1000
Input Clock
csb_clk :
Ratio
10 : 1
11 : 1
12 : 1
13 : 1
14 : 1
15 : 1
16 : 1
10 : 1
12 : 1
14 : 1
16 : 1
2 : 1
3 : 1
4 : 1
5 : 1
6 : 1
7 : 1
8 : 1
9 : 1
4 : 1
6 : 1
8 : 1
2
16.67
100
116
133
150
166
183
200
216
233
250
266
100
133
166
200
233
266
Input Clock Frequency (MHz)
csb_clk Frequency (MHz)
100
125
150
175
200
225
250
275
300
325
100
150
200
250
300
25
33.33
100
133
166
200
233
266
300
333
133
200
266
333
66.67
2
133
200
266
333
266
Clocking
81