MC68MH360AI33L Freescale Semiconductor, MC68MH360AI33L Datasheet - Page 68

• Manufacturer Part Number: MC68MH360AI33L
• Description: IC MPU QUICC 33MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360AI33L

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 33MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

3
4
5–9
10
11
12
13
Field
IDL
Channel
Number
MRF
UN
RXF
BSY
Name
Table 4-2. Interrupt Table Entry Field Descriptions (Continued)
Idle
0 = No IDL event has occurred.
1 = The channel’s receiver has identified the first occurrence of HDLC idle (FFFE) after any
IDL interrupts are not generated in transparent mode.
Reserved
This 5-bit field identifies the requesting logical channel index (0–31).
Maximum receive frame length violation—This interrupt occurs in HDLC mode when more
than MFLR number bytes are received. As soon as MFLR is exceeded, this interrupt is
generated and the remainder of the frame is discarded. At this point the receive buffer is not
closed and the reception process continues. The receive buffer is closed upon detecting a
flag. The length field written to this buffer descriptor is the entire number of bytes received
between the two flags.
MRF interrupts are not generated in transparent mode.
Note: The MRF interrupt is generated directly when the MFLR value is a multiple of 4 bytes.
The checking of this is done on a long-word boundary whenever the SDMA transfers 32 bits to
memory. If MFLR is not aligned to 4x bytes, this interrupt may be 1- to 3-byte timings late for
this channel. In any case, the violation can be checked to any number of bytes. The last entry
in the data buffer is always a full long word.
Tx no data
0 = No UN event has occurred.
1 = There is no valid data to send to the transmitter. The transmitter sends an abort indication
0 = No RXF event has occurred.
1 = A complete HDLC frame is received. Data is stored in external memory and the buffer
As a result of end-of-frame, the global frame counter GRFCNT is decremented for interrupt
generation. This counter is decremented on RXF only, regardless if the RXF was caused by
correct closing or due to an error.
RXF interrupts are not generated in transparent mode.
Busy
0 = No BSY event has occurred.
1 = A frame was received but was discarded due to lack of buffers. This can be viewed as
Rx frame
Freescale Semiconductor, Inc.
non-idle pattern.
consisting of 16 consecutive 1’s and then sends idles or flags according to the protocol and
the channel mode register setting. This error occurs when a transmit channel has no data
buffer ready for a multibuffer transmission already in progress. Transmission of a frame is a
continuous bitstream without gaps or interruption. When a buffer is not ready in the middle
of this sequence, it is an error situation. This can be viewed as channel underrun. The
transmitter for this channel is stopped. See Section 6.3, “Restarting the Transmitter,” for
recovery information.
descriptor is updated. If during frame reception an abort sequence of at least seven 1’s is
detected, the buffer is closed and both RXB and RXF are reported along with the AB in the
buffer descriptor.
channel overrun. After a busy condition, the receiver for this channel is disabled and no
more data is transferred to memory. Receiver restart is described in Section 6.4,
“Restarting the Receiver.”
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QMC Supplement
Description