MC68MH360AI33L Freescale Semiconductor, MC68MH360AI33L Datasheet - Page 45

• Manufacturer Part Number: MC68MH360AI33L
• Description: IC MPU QUICC 33MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360AI33L

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 33MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

MODE
Reset:
2.4.1.1 CHAMR—Channel Mode Register (HDLC)
The channel mode register is a word-length, host-initialized register. Figure 2-7 shows the
channel mode register for HDLC operation.
22
24
28
2C
2E
30
34
38
3C
3E
Offset
0
0
Notes: 1. All bits that are defined as reserved should be cleared (0).
1
0
0
MFLR
RSTATE
—
RBPTR
—
RPACK
ZDSTATE
RCRC
MAX_cnt
TMP_MB
2. For the 68360, the bit numbering is reversed. See Appendix A for more information.
Name
IDLM
Table 2-4. Channel-Specific HDLC Parameters (Continued)
2
0
Figure 2-7. CHAMR—Channel Mode Register (HDLC)
ENT
Freescale Semiconductor, Inc.
3
0
Width
16
32
32
16
16
32
32
32
16
16
(Bits)
For More Information On This Product,
4
0
Maximum frame length register (host-initialized)—Defines the longest expectable
frame for this channel. Its maximum value is 64 Kbytes. The remainder of a frame
which is larger than MFLR is discarded and a flag in the last frame’s BD is set (LG).
An interrupt request (RXF and RXB) might be generated depending on the
interrupt mask. The frame length is considered to be everything between flags,
including CRC. MFLR is checked every long word, but the content may be on any
number of bytes. If MFLR is set to 5 for example, checking is done when 8 bytes
have been received. At this point, the SDMA transfers the long word to memory,
and all 8 bytes will be in the receive buffer. Also at this point the MFLR violation
(>5) is detected and the interrupt may be generated.
No more data will be written into this buffer when the MFLR violation is detected.
Rx internal state —Initialize to 0x3900
initialize to 0x3100
“RSTATE—Rx Internal State (HDLC),” for more information.
Rx internal data pointer—Points to current address of specific channel.
Rx buffer descriptor pointer (host-initialized to RBASE prior to operation or due to a
fatal error)—Contains the offset from MCBASE to the current receive buffer. See
Table 2-1. MCBASE + RBPTR gives the address for the BD in use.
Rx internal byte count—Per Channel: Number of remaining bytes in buffer
(Rx Temp) Packs 4 bytes to 1 long word before writing to buffer.
Zero deletion machine state—(Host-initialized to 0x0000
0x1800
(global overrun, busy) before channel initialization.)—Contains the previous state
of zero deletion state machine.
The middle 2 bytes, represented by zeros in the initialization value above, hold the
received pattern during reception. A window of 16 bits shows the history of what is
received on this logical channel. More information is given in the application note
section.
Temp receive CRC—Temp value of CRC calculation result
Max_length counter—Count length remaining
Temp—Holds MIN(MAX_cnt, Rx internal byte count)
RESERVED
Chapter 2. QMC Memory Organization
5
0
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_
0080 in transparent mode, prior to operation and after a fatal Rx error
6
0
_
POL
0000 AT=1, Motorola mode for 860MH. See Section 2.4.1.4,
7
0
CRC
8
0
Description
9
0
0
_
0000 FC=9, Motorola mode for MH360 or
10
RESERVED
0
11
0
_
12
0080 in HDLC mode,
0
13
0
NOF
14
0
15
0