MC68MH360AI33L Freescale Semiconductor, MC68MH360AI33L Datasheet - Page 34

• Manufacturer Part Number: MC68MH360AI33L
• Description: IC MPU QUICC 33MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360AI33L

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 33MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

2.1.4 TSATRx/TSATTx Channel Pointers
The channel pointers are 12-bit pointers to the channel-specific parameters in the internal
dual-ported RAM. These should not be confused with TSATRx/TSATTx pointers as
described in Section 2.1.3, “TSATRx/TSATTx Pointers and Time Slot Assignment Table.”
The 6 most-significant bits of the address are taken from the time slot assignment table. For
the MH360, the most-significant bit must be zero as the addressing range is only 2 Kbytes.
The 6 least-significant bits are zero, mapping out a 64-byte area for each of the channel-
specific parameters. The channel-specific parameters are common for Rx and Tx. For 32-
channel support, 2 Kbytes of dual-ported RAM is required (32 * 64), and for 64-channel
support, 4 Kbytes of dual-ported RAM is required (64 * 64). In most cases, time slot 0
channel pointer will address the base of dual-ported RAM for logical channel 0, and time
slot 1 channel pointer would address the base of dual-ported RAM + 4 for logical channel 1.
In Figure 2-2, time slot 5 channel pointer addresses logical channel 5, requiring the channel
pointer being set to 0b000101.
2.1.5 Logical Channel TBASE and RBASE
TBASE and RBASE are within the channel-specific parameters. TBASE is the Tx buffer
descriptor base address, and RBASE is the Rx buffer descriptor base address. These 16-bit
offsets from MCBASE point to individual logical channel’s buffer descriptors located
within the buffer descriptor table. Note that there are individual TBASE and RBASE values
for each logical channel.
2.1.6 MCBASE
MCBASE is located in the global multichannel parameters. Each SCC has a unique
MCBASE value pointing to the base of the SCC’s buffer descriptor table in external
memory. For example, the address of logical channel five’s Tx buffer descriptor table is
MCBASE + logical channel five TBASE.
2.1.7 Buffer Descriptor Table
A buffer descriptor table for each SCC is located in a 64-Kbyte area of external memory.
This block size is determined by the TBASE and RBASE addressing range. The memory
segment must be long-word-aligned but can start anywhere in memory. Each SCC has a
maximum of 16,384 (64 Kbytes memory
implementation, each logical channel has a maximum of 256 (16,384 / (32 * 2)) buffers for
receive and 256 buffers for transmit. For each logical channel, there is a circular queue with
programmable start address and length.
It is possible to concatenate multiple time slots to one logical
channel. This is achieved by setting the channel pointers of the
grouped time slots to the same logical channel.
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
QMC Supplement
NOTE
4-byte pointers) buffers. For a 32-channel