MPC5200CVR400 Freescale Semiconductor, MPC5200CVR400 Datasheet - Page 18

IC MPU 32BIT 400MHZ PPC 272-PBGA

MPC5200CVR400

Manufacturer Part Number
MPC5200CVR400
Description
IC MPU 32BIT 400MHZ PPC 272-PBGA
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MPC5200CVR400

Processor Type
MPC52xx PowerPC 32-Bit
Speed
400MHz
Voltage
1.5V
Mounting Type
Surface Mount
Package / Case
272-PBGA
Family Name
MPC52xx
Device Core
PowerPC
Device Core Size
32b
Frequency (max)
400MHz
Instruction Set Architecture
RISC
Operating Supply Voltage (max)
1.58V
Operating Supply Voltage (min)
1.42V
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
272
Package Type
BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Compliant

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Electrical and Thermal Characteristics
3.3.4
The MPC5200 provides three different kinds of external interrupts:
The propagation of these three kinds of interrupts to the core is shown in the following graphic:
Due to synchronization, prioritization, and mapping of external interrupt sources, the propagation of
external interrupts to the core processor is delayed by several IP_CLK clock cycles. The following table
specifies the interrupt latencies in IP_CLK cycles. The IP_CLK frequency is programmable in the Clock
Distribution Module (see Note
18
Interrupt Requests
IRQ0
8 GPIOs
8 GPIOs
IRQ1
IRQ2
IRQ3
Four IRQ interrupts
Eight GPIO interrupts with simple interrupt capability (not available in power-down mode)
Eight WakeUp interrupts (special GPIO pins)
Interrupt Type
External Interrupts
Beware of changing the values on the pins of the reset configuration word
after the deassertion of PORRESET. This may cause problems because it
may change the internal clock ratios and so extend the PLL locking process.
8
8
Notes:
1. PIs = Programmable Inputs
2. Grouper and Encoder functions imply programmability in software
GPIO WakeUp
GPIO Std
Pin Name
Table
IRQ0
IRQ0
IRQ1
IRQ2
IRQ3
Table 16. External interrupt latencies
Figure 4. External interrupt scheme
16).
MPC5200 Data Sheet, Rev. 4
Clock Cycles
NOTE
10
10
10
10
10
cint
int
PIs
Main Interrupt
Controller
Reference Clock
IP_CLK
IP_CLK
IP_CLK
IP_CLK
IP_CLK
Encoder
Grouper
Encoder
Core Interrupt
critical (cint)
normal (int)
normal (int)
normal (int)
normal (int)
Freescale Semiconductor
core_cint
core_int
G2_LE Core
SpecID
A4.1
A4.2
A4.3
A4.5
A4.6

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