MPC5200CVR400B Freescale Semiconductor, MPC5200CVR400B Datasheet - Page 66

• Manufacturer Part Number: MPC5200CVR400B
• Description: IC MPU 32BIT 400MHZ 272-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC5200CVR400B

• Processor Type: MPC52xx PowerPC 32-Bit
• Speed: 400MHz
• Voltage: 1.5V
• Mounting Type: Surface Mount
• Package / Case: 272-PBGA
• Processor Series: MPC52xx
• Core: e300
• Development Tools By Supplier: MEDIA5200KIT1E
• Maximum Clock Frequency: 400 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• I/o Voltage: 2.5 V, 3.3 V
• Minimum Operating Temperature: - 40 C
• Core Size: 32 Bit
• No. Of I/o's: 56
• Ram Memory Size: 16KB
• Cpu Speed: 400MHz
• No. Of Timers: 8
• Embedded Interface Type: CAN, I2C, SCI, SPI
• No. Of Pwm Channels: 8
• Digital Ic Case Style: TEPBGA
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

3.3.2
If the PCI interface is NOT used (and internally disabled) the PCI control pins must be terminated as indicated by the PCI Local
Bus specification. This is also required for MOST/Graphics and Large Flash Mode.
PCI control signals always require pull-up resistors on the motherboard (not the expansion board) to ensure that they contain
stable values when no agent is actively driving the bus. This includes PCI_FRAME, PCI_TRDY, PCI_IRDY, PCI_DEVSEL,
PCI_STOP, PCI_SERR, PCI_PERR, and PCI_REQ.
3.3.3
The MEM_MDQS[3:0] signals are not used with SDR memories and require pull-up or pull-down resistors in SDRAM mode.
3.3.4
The MEM_MDQS[1:0] signals are not used in DDR 16-bit mode and require pull-down resistors.
3.4
The MPC5200B provides the user an IEEE 1149.1 JTAG interface to facilitate board/system testing. It also provides a Common
On-Chip Processor (COP) Interface, which shares the IEEE 1149.1 JTAG port. The COP Interface provides access to the
MPC5200B's embedded Freescale (formerly Motorola) MPC603e e300 processor. This interface provides a means for
executing test routines and for performing software development and debug functions.
3.4.1
Boundary scan testing is enabled through the JTAG interface signals. The JTAG_TRST signal is optional in the IEEE 1149.1
specification but is provided on all processors that implement the PowerPC architecture. To obtain a reliable power-on reset
performance, the JTAG_TRST signal must be asserted during power-on reset.
3.4.1.1
The JTAG interface can control the direction of the MPC5200B I/O pads via the boundary scan chain. The JTAG module must
be reset before the MPC5200B comes out of power-on reset; do this by asserting JTAG_TRST before PORRESET is released.
For more details refer to the Reset and JTAG Timing Specification.
3.4.1.2
The wiring of the JTAG_TRST depends on the existence of a board-related debug interface. (see below)
66
Required assertion of JTAG_TRST
JTAG_TRST
PORRESET
JTAG
Pull-up Requirements for the PCI Control Lines
Pull-up/Pull-down Requirements for MEM_MDQS Pins (SDRAM)
.
Mode)
JTAG_TRST
Pull-up/Pull-down Requirements for MEM_MDQS Pins (DDR 16-bit
JTAG_TRST and PORRESET
Connecting JTAG_TRST
Figure 53. PORRESET vs. JTAG_TRST
MPC5200B Data Sheet, Rev. 4
Optional assertion of JTAG_TRST
Freescale Semiconductor