MPC5200CVR400B Freescale Semiconductor, MPC5200CVR400B Datasheet - Page 14

• Manufacturer Part Number: MPC5200CVR400B
• Description: IC MPU 32BIT 400MHZ 272-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC5200CVR400B

• Processor Type: MPC52xx PowerPC 32-Bit
• Speed: 400MHz
• Voltage: 1.5V
• Mounting Type: Surface Mount
• Package / Case: 272-PBGA
• Processor Series: MPC52xx
• Core: e300
• Development Tools By Supplier: MEDIA5200KIT1E
• Maximum Clock Frequency: 400 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• I/o Voltage: 2.5 V, 3.3 V
• Minimum Operating Temperature: - 40 C
• Core Size: 32 Bit
• No. Of I/o's: 56
• Ram Memory Size: 16KB
• Cpu Speed: 400MHz
• No. Of Timers: 8
• Embedded Interface Type: CAN, I2C, SCI, SPI
• No. Of Pwm Channels: 8
• Digital Ic Case Style: TEPBGA
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

1.3.4
The MPC5200B has three reset pins:
These signals are asynchronous I/O signals and can be asserted at any time. The input side uses a Schmitt trigger and requires
the same input characteristics as other MPC5200B inputs, as specified in the DC Electrical Specifications section.
specifies the pulse widths of the Reset inputs.
For PORRESET the value of the minimum pulse width reflects the power on sequence. If PORRESET is asserted afterwards
its minimum pulse width equals the minimum given for HRESET related to the same reference clock.
The t
For t
For t
Following the deassertion of PORRESET, HRESET and SRESET remain low for 4096 reference clock cycles.
The deassertion of HRESET for at least the minimum pulse width forces the internal resets to be active for an additional 4096
clock cycles.
14
•
•
•
lock,
up_osc,
VDD_stable
PORRESET
HRESET
SRESET
PORRESET—Power on Reset
HRESET—Hard Reset
SRESET—Software Reset
Name
refer to the Oscillator/PLL section of this specification for further details.
refer to the Oscillator/PLL section of this specification for further details.
Resets
describes the time which is needed to get all power supplies stable.
As long as VDD is not stable the HRESET output is not stable.
Make sure that the PORRESET does not carry any glitches. The MPC5200B has no filter
to prevent them from getting into the chip. HRESET and SRESET must have a monotonous
rise time. The assertion of HRESET becomes active at Power on Reset without any
SYS_XTAL clock.
Power On Reset
Hardware Reset
Software Reset
Description
PORRESET rise time
PORRESET fall time
HRESET rise time
SRESET rise time
HRESET fall time
SRESET fall time
Description
t
VDD_stable
Table 15. Reset Rise/Fall Timing
Min Pulse Width
Table 14. Reset Pulse Width
4 clock cycles
4 clock cycles
MPC5200B Data Sheet, Rev. 4
+ t
up_osc
NOTE
NOTE
+ t
lock
Max Pulse
Min
—
—
—
—
—
—
Width
—
—
—
Max
1
1
1
1
1
1
Reference Clock
SYS_XTAL_IN
SYS_XTAL_IN
SYS_XTAL_IN
Unit
ms
ms
ms
ms
ms
ms
Freescale Semiconductor
SpecID
A3.4
A3.5
A3.6
A3.7
A3.8
A3.9
SpecID
A3.1
A3.2
A3.3
Table 14