Z9025106PSC Zilog, Z9025106PSC Datasheet - Page 57

• Manufacturer Part Number: Z9025106PSC
• Description: IC 32K 8BIT DTC OTP 42-DIP
• Manufacturer: Zilog

Specifications of Z9025106PSC

• Applications: TV Controller
• Core Processor: Z8
• Program Memory Type: OTP (32 kB)
• Controller Series: Digital Television Controller (DTC)
• Ram Size: 300 x 8
• Interface: I²C, 2-Wire Serial
• Number Of I /o: 27
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 42-DIP (0.600", 15.24mm)
• Processor Series: Z902x
• Core: Z8
• Data Bus Width: 8 bit
• Program Memory Size: 32 KB
• Data Ram Size: 300 B
• Interface Type: I2C
• Maximum Clock Frequency: 6 MHz
• Number Of Programmable I/os: 27
• Mounting Style: Through Hole
• On-chip Adc: 4 bit, 4 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

5.10 HV Interrupt Processing
Row Attribute Register
The Row Attribute Register (Table 33) is mapped to VRAM, as shown in Table 20.
This register controls row background and foreground display. If the Color Index is
set to 000h, the display color is read from the Row Attribute Register.
Table 33 Row Attribute Register (ROW_ATTR)
An interrupt is issued at the beginning of a row and at the leading edge of the
V
beginning of a row. The Z90255 software tracks this cycle as two recurring events,
the Horizontal (H
A V
Displaying subsequent rows coincides with the issuance of the H
The interrupts mark the time when displaying a row or start of a field is to occur.
Each text row is comprised of 18 scan lines. Each scan line takes 63.5 µs to be
displayed. So, 1143 µs is the amount of time available to change programming for
the next row. Double-size and double-height characters span 36 scan lines,
Bit
R/W
Reset
Note: R = Read W = Write X = Indeterminate
Bit/
Field
Row Foreground
Enable
Row Foreground
Color
Row Background
Enable
Row Background
Color
SYNC
SYNC
signal. The leading edge of the first H
interrupt marks the time for displaying a new field of a TV frame.
7
SYNC
R/W
x
Bit
Position R/W
7
6, 5, 4
3
2, 1, 0
) Interrupt and the Vertical (V
6
R/W
x
R/W
R/W
R/W
R/W
5
R/W
x
Value Description
4
0
1
0
1
32 KB Television Controller with OSD
R/W
x
SYNC
Row Foreground Color displayed
Row Foreground color disabled
Defines the Character Color R, G, B,
respectively
Row Background Color disabled
Row Background color displayed
Defines the Row Background Color R,
G, B, respectively
3
of a row constitutes the
R/W
SYNC
x
) Interrupt.
2
R/W
x
SYNC
1
R/W
PS001301-0800
x
interrupt.
0
R/W
x
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