Z9025106PSC Zilog, Z9025106PSC Datasheet - Page 25

• Manufacturer Part Number: Z9025106PSC
• Description: IC 32K 8BIT DTC OTP 42-DIP
• Manufacturer: Zilog

Specifications of Z9025106PSC

• Applications: TV Controller
• Core Processor: Z8
• Program Memory Type: OTP (32 kB)
• Controller Series: Digital Television Controller (DTC)
• Ram Size: 300 x 8
• Interface: I²C, 2-Wire Serial
• Number Of I /o: 27
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 42-DIP (0.600", 15.24mm)
• Processor Series: Z902x
• Core: Z8
• Data Bus Width: 8 bit
• Program Memory Size: 32 KB
• Data Ram Size: 300 B
• Interface Type: I2C
• Maximum Clock Frequency: 6 MHz
• Number Of Programmable I/os: 27
• Mounting Style: Through Hole
• On-chip Adc: 4 bit, 4 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

4.2
Note:
execute a NOP instruction (opcode = FFh) immediately before the Halt instruction
(opcode 7Fh), that is,
The Halt Mode is exited by interrupts, generated either externally or internally.
When the interrupt service routine is completed, the user program continues from
the instruction after Halt.
The Halt Mode can also be exited via a POR/Reset activation or a Watch-Dog
Timer (WDT) timeout. In this case, program execution restarts at the reset-restart
address 000Ch.
To reduce power consumption further in the Halt Mode, the Z90255 and Z90251
allow dynamic internal clock scaling. Clock scaling can be accomplished on the fly
by reprogramming bit 0 and/or bit 1 of the Stop-Mode Recovery register (SMR).
Stop Mode Operation
The Stop Mode provides the lowest possible device standby current. This
instruction turns off the on-chip oscillator and internal system clock.
To enter the Stop Mode, the instruction pipeline must be flushed first to avoid
suspending execution in mid-instruction. To do this, the application program must
execute a NOP instruction (opcode=FFh) immediately before the Stop instruction
(opcode=6Fh), that is,
The Stop Mode is exited by any one of the following resets: Power-On Reset
activation, WDT timeout, or a Stop-Mode Recovery source. When reset is
generated, the processor always restarts the application program at address
000Ch.
POR/Reset activation is present on the Z90255 and Z90251 and is implemented
as a reset pin and/or an on-chip power on reset circuit.
When the WDT is configured to run during Stop mode, the WDT timeout
generates a Reset ending Stop Mode.
FF
6F
FF
7F
Internal clock scaling directly effects Counter/Timer operation:
adjustment of the prescaler and downcounter values might be
required.
NOP
Stop
NOP
Halt
;clear the instruction pipeline
;enter Stop Mode
;clear the instruction pipeline
;enter Halt Mode
32 KB Television Controller with OSD
PS001301-0800
17