Z9025106PSC Zilog, Z9025106PSC Datasheet - Page 28

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Z9025106PSC

Manufacturer Part Number
Z9025106PSC
Description
IC 32K 8BIT DTC OTP 42-DIP
Manufacturer
Zilog
Datasheet

Specifications of Z9025106PSC

Applications
TV Controller
Core Processor
Z8
Program Memory Type
OTP (32 kB)
Controller Series
Digital Television Controller (DTC)
Ram Size
300 x 8
Interface
I²C, 2-Wire Serial
Number Of I /o
27
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Through Hole
Package / Case
42-DIP (0.600", 15.24mm)
Processor Series
Z902x
Core
Z8
Data Bus Width
8 bit
Program Memory Size
32 KB
Data Ram Size
300 B
Interface Type
I2C
Maximum Clock Frequency
6 MHz
Number Of Programmable I/os
27
Mounting Style
Through Hole
On-chip Adc
4 bit, 4 Channel
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Figure 7 illustrates Stop Mode Recovers Source/Level Select.
Table 7
External Clock Divide-by-Two
(bit 1)
Stop-Mode Recovery Source
(bits 2, 3, and 4)
Stop Mode Recovery Delay
Select (bit 5)
4
0
0
0
1
1
1
Bits
3
0
0
1
0
1
1
Stop Mode Recovery Source
2
0
1
0
1
0
1
Operation
POR and/or external reset recovery
P63 transition
P62 transition (not in Analog Mode)
P27 transition
Logical NOR of P20 through P23
Logical NOR of P20 through P27
Description of Action
This bit can eliminate the oscillator divide-by-
two circuitry. When this bit is 0, the System
Clock (SCLK) and Timer Clock (TCLK) are
equal to the external clock frequency divided by
two. The SCLK/TCLK is equal to the external
clock frequency when this bit is set (D1=1).
Using this bit together with D7 of PCON helps
lower EMI (D7 (PCON) =0, D1 (SMR) =1). The
default setting is zero.
These three bits specify the wake-up source of
the Stop-Mode recovery.
This bit, if High, enables the T
after Stop Mode Recovery. The default
configuration of this bit is 1. If the fast wake up
is selected, the Stop Mode Recovery source is
kept active for at least 5 TpC.
32 KB Television Controller with OSD
POR
PS001301-0800
Reset delay
20

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