CY7C63743-SXC Cypress Semiconductor Corp, CY7C63743-SXC Datasheet - Page 8

• Manufacturer Part Number: CY7C63743-SXC
• Description: IC MCU 8K USB/PS2 LS 24SOIC
• Manufacturer: Cypress Semiconductor Corp
• Series: enCoRe™r

Specifications of CY7C63743-SXC

• Applications: USB Microcontroller
• Core Processor: M8B
• Program Memory Type: OTP (8 kB)
• Controller Series: CY7C637xx
• Ram Size: 256 x 8
• Interface: PS2, USB
• Number Of I /o: 16
• Voltage - Supply: 4 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 24-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 428-1622

8.2
The CY7C637xx microcontrollers provide 256 bytes of data
RAM. In normal usage, the SRAM is partitioned into four
areas: program stack, data stack, user variables and USB
endpoint FIFOs as shown below.
8.3
I/O registers are accessed via the I/O Read (IORD) and I/O
Write (IOWR, IOWX) instructions. IORD reads the selected
port into the accumulator. IOWR writes data from the accumu-
lator to the selected port. Indexed I/O Write (IOWX) adds the
contents of X to the address in the instruction to form the port
address and writes data from the accumulator to the specified
Table 8-1. I/O Register Summary
Document #: 38-08022 Rev. *B
Port 0 Data
Port 1 Data
Port 2 Data
Port 0 Interrupt Enable
Port 1 Interrupt Enable
Port 0 Interrupt Polarity
Port 1 Interrupt Polarity
Port 0 Mode0
Port 0 Mode1
Port 1 Mode0
Port 1 Mode1
8-bit DSP
8-bit DSP
Register Name
Data Memory Organization
I/O Register Summary
(User’s firmware moves DSP)
After reset
8-bit PSP
Top of RAM Memory
I/O Address
0x0A
0x0B
0x0C
0x0D
0x00
0x01
0x02
0x04
0x05
0x06
0x07
FOR
FOR
Figure 8-2. Data Memory Organization
User Selected
Address
0xE8
0xF0
0xF8
0xFF
0x00
Read/Write
R/W
R/W
W
W
W
W
W
W
W
W
R
User Variables
USB FIFO for Address A endpoint 2
USB FIFO for Address A endpoint 1
USB FIFO for Address A endpoint 0
GPIO Port 0
GPIO Port 1
Auxiliary input register for D+, D–, VREG, XTALIN
Interrupt enable for pins in Port 0
Interrupt enable for pins in Port 1
Interrupt polarity for pins in Port 0
Interrupt polarity for pins in Port 1
Controls output configuration for Port 0
Controls output configuration for Port 1
port. Note that specifying address 0 with IOWX (e.g., IOWX
0h) means the I/O port is selected solely by the contents of X.
Note: All bits of all registers are cleared to all zeros on
reset, except the Processor Status and Control Register
(Figure 20-1). All registers not listed are reserved, and should
never be written by firmware. All bits marked as reserved
should always be written as 0 and be treated as undefined by
reads.
Program Stack Growth
Data Stack Growth
Function
CY7C63722
CY7C63723
CY7C63743
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