XE8802MI035LF Semtech, XE8802MI035LF Datasheet - Page 108

• Manufacturer Part Number: XE8802MI035LF
• Description: IC DAS 16BIT FLASH 8K 100-LQFP
• Manufacturer: Semtech

Specifications of XE8802MI035LF

• Applications: Sensing Machine
• Core Processor: RISC
• Program Memory Type: FLASH (22 kB)
• Controller Series: XE8000
• Ram Size: 1K x 8
• Interface: SPI, UART
• Number Of I /o: 36
• Voltage - Supply: 2.4 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• For Use With: XE8000MP - PROG BOARD AND PROSTART2 CARD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The transmission format depends on the two configuration bits ClockPhase and ClockPolarity. These 2 bits
should be configured in the same way in the slave and the master device in order to properly run the SPI
transmission. The transmission baud rate depends on the two bits BaudRate, these 2 bits are only used in the
master device to generate the serial clock SCK signal at the selected frequency. Data are transferred in a duplex
way from master to slave through the MOSI wire and from slave to master through the MISO wire. Data are always
sent most significant bit first. Each SPI device sequentially operates in two times: one clock edge to sample the
received bit, and the other clock edge to shift the byte inside the shift register. The NSS signal is software
controlled. It must be driven by the SPI master device by writing to the bit NotSlaveSelect in RegSpiControl. NSS
should remain low during the byte transmission.
The next figure shows the timing diagrams for a SPI transmission with ClockPhase equal to 0. This means the
active state of the serial clock SCK signal occurs on the 2
The next figure shows the timing diagrams for a SPI transmission with ClockPhase equal to 1. This means the
active state of the serial clock SCK signal occurs on the 1
© Semtech 2006
SCK cycle
SCK
(CPOL=0)
SCK
(CPOL=1)
MOSI
MISO
NSS
Shift register
Baud Rate
Generator
Master
MSB
MSB
1
Figure 16-2: SPI transmission format with ClockPhase=0
bit 6
bit 6
2
MISO
MOSI
SCK
NSS
16-1: Connection of master and slave device
bit 5
bit 5
3
XE8802 Sensing Machine Data Acquisition MCU
bit 4
bit 4
4
bit 3
bit 3
5
16-5
nd
st
half of the SCK cycle.
half of the SCK cycle.
with ZoomingADC™ and LCD driver
bit 2
bit 2
6
MISO
MOSI
SCK
NSS
bit 1
bit 1
7
LSB
LSB
8
Shift register
Slave
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Figure