XE8802MI035LF Semtech, XE8802MI035LF Datasheet - Page 106

• Manufacturer Part Number: XE8802MI035LF
• Description: IC DAS 16BIT FLASH 8K 100-LQFP
• Manufacturer: Semtech

Specifications of XE8802MI035LF

• Applications: Sensing Machine
• Core Processor: RISC
• Program Memory Type: FLASH (22 kB)
• Controller Series: XE8000
• Ram Size: 1K x 8
• Interface: SPI, UART
• Number Of I /o: 36
• Voltage - Supply: 2.4 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• For Use With: XE8000MP - PROG BOARD AND PROSTART2 CARD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Block configuration registers:
Note that the precision of the 4kHz depends on the selected clock source (see documentation of the clock block).
In slave mode, the fastest clock of the circuit should be at least 4 times faster than the baud rate of the master.
© Semtech 2006
7
6
5
4
3
2
1-0
7-3
2
1
0
7-0
Pos.
pos.
pos.
ClearCounter
SpiEnable
ClockPhase
ClockPolarity
SpiDataOut[7:0]
NotSlaveSelect
SpiMaster
BaudRate
--
SpiOverflow
SpiRxFull
SpiTxEmpty
RegSpiDataOut
RegSpiControl
RegSpiStatus
r/w
w1
r/w
r/w
r/w
r/w
r/w
r/w
r
r
c1
r
r
w1
Rw
Rw
Rw
00000000
-
1 nresetglobal
1 nresetglobal
0 nresetglobal
1 nresetglobal
0 nresetglobal
00
nresetglobal
00000
0
nresetglobal
0
nresetglobal
1
nresetglobal
nresetglobal
XE8802 Sensing Machine Data Acquisition MCU
Table 16-5: RegSpiDataOut
Table 16-3: RegSpiControl
Table 16-4: RegSpiStatus
Reset
Reset
Reset
16-3
Writing 1 clears transmission control counters.
In master mode, this bit drives the NSS output
pad. Unused in slave mode. It must be
asserted (to 0) during a byte transfer.
0: SPI slave mode.
1: SPI master mode.
peripheral configuration:
0: general purpose digital I/O port
1: SPI interface
Controls the timing relationship between the
serial clock and SPI data (cf. Figure 16-2 and
Figure 16-3).
Determines the idle-state of the SPI clock
signal (cf. Figure 16-2 and Figure 16-3).
Selects the baud rate in master mode.
00 => ckRcExt/2
01 => ckRcExt/8
10 => ckRcExt/16
11 => 4kHz
Unused
This flag is set when a new byte is loaded in
SpiDataIn before the previous byte was read.
Writing 1 clears the flag.
This flag is set each time a byte transfers from
the shift register to SpiDataIn. It is cleared by
reading SpiDataIn.
This flag is cleared each time the CPU writes a
byte in SpiDataOut. It is set when a byte
transfers from SpiDataOut to the shift register.
In the master mode, writing 1 to this bit
performs the data transfer SpiDataOut to the
shift
transmission.
In the slave mode, the byte transfer is done
automatically except for the very first byte
after nresetglobal (cf.16.6 Software hints).
SPI mode: transmission data buffer
I/O mode: output data (only bits 3:0, see Table
16-2)
with ZoomingADC™ and LCD driver
register
and
Function
Function
Function
enables
the
start
www.semtech.com
of