FMS7401LEN14 Fairchild Semiconductor, FMS7401LEN14 Datasheet - Page 8

• Manufacturer Part Number: FMS7401LEN14
• Description: IC CTRLR POWER DGTL EEPROM 14DIP
• Manufacturer: Fairchild Semiconductor

Specifications of FMS7401LEN14

• Applications: Digital Power Controller
• Core Processor: 8-Bit
• Program Memory Type: EEPROM (1 kB)
• Ram Size: 64 x 8
• Number Of I /o: 8
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Through Hole
• Package / Case: 14-DIP (0.300", 7.62mm)
• Output Current: 5 mA
• Input Voltage: 2.7 V to 3.6 V
• Switching Frequency: 2 MHz
• Operating Temperature Range: - 40 C to + 85 C
• Mounting Style: Through Hole
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Interface: -
• Controller Series: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: FMS7401LEN14_NL; FMS7401LEN14_NL

FMS7401L
1
The reset circuit in the FMS7401L contains four input conditions that trigger a main system reset. When the main system reset
is triggered, a sequence of events occur defaulting all memory mapped registers (including the initialization registers) and I/Os
to their initial states (see
the internal oscillator and other analog circuits to stabilize. Once the system reset sequence completes, the device will begin
with its normal operation executing the instruction program residing in the code EEPROM memory. The time required for the
system reset sequence to complete (T
Characteristics
• Power-on Reset (POR)
• External Reset
• Brown-out Reset (BOR)
• Watchdog Reset
Table 1. Default Register States
1.1
The Power-on Reset (POR) circuit maintains the device in a reset state until Vcc reaches a voltage level high enough to guaran-
tee proper device operation. The POR circuit is sensitive to the different Vcc ramp rates and must be within S
the
The POR circuit does not generate a system reset when Vcc is falling. This feature is performed by the Brown-out Reset (BOR)
circuit and must be enabled by the BOREN bit of the Initialization Register 1.
before the next power-up sequence, it is necessary to enable the BOR circuit and/or reset the device externally through the
RESET pin.
1.2
The device may be externally reset through the RESET input pin if the POR/BOR circuits cannot be used to properly reset the
device in the application. The RESET input pin contains an internal pull-up resistor making it an active low signal. Therefore,
to issue a device system reset the RESET input should be held low for at least 10µS before being released (i.e. returned to a
high state). While the RESET input is held low, the internal oscillator and other analog circuits are kept in a low power state
reducing the current consumption of the device (a state resembling Halt Mode). In addition, the I/O pins are all initialized to an
input tri-state configuration unless defaulted otherwise.
sequence is triggered releasing the internal oscillator and other analog circuits so that they may be initialized and begin their
normal operation.
1.3
The Brown-out Reset (BOR) circuit is one of the on-chip analog comparator peripherals and must be enabled through the
BOREN bit of the Initialization Registers 1.
a fixed threshold defined in the
condition until Vcc rises above the fixed/power-on threshold. Shortly after Vcc rises above the fixed/power-on threshold, the
internal system reset sequence is started. Once the system reset sequence completes, the device will begin with its normal
operation executing the instruction program residing in the code EEPROM memory.
8
G1, G2, G3, G4, G6, G7
G0, G5
SRAM Memory
Stack Pointer
Status Register
T1CMPA, T1CMPB and T1RA Registers
DTIME Register
All other memory mapped register not listed above.
Electrical Characteristics
Reset Circuit
Power-on Reset Circuit
External Reset
Brown-out Reset Circuit
1
section of the datasheet. The four reset trigger conditions are as follows:
1
2
Peripheral/Register
Table
1
section of the datasheet.
1). During the system reset sequence, the instruction core execution is halted allowing time for
Electrical Characteristics
RESET
) is dependent on the individual trigger condition and is defined in the
4
The BOR circuit is used to hold the device in a reset state when Vcc drops below
3
5
At the rising edge of the RESET input signal, the main system reset
section of the datasheet. While in reset, the device is held in its initial
External Reset
No change
0xFFF
0x80
0x1F
0x00
High-impedance input (tri-state input)
0xF
Defined by Init Reg. 4 (see
4
In the case where Vcc does not drop to 0V
PRODUCT SPECIFICATION
Table
Unspecified
REV. 1.0.3 1/24/05
28)
Vcc
0xFFF
POR
0x80
0x1F
0x00
0xF
as specified in
Electrical