EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 74

• Manufacturer Part Number: EP2AGX45DF29I5N
• Description: IC ARRIA II GX FPGA 45K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX45DF29I5N

• Number Of Logic Elements/cells: 42959
• Number Of Labs/clbs: 1805
• Total Ram Bits: 3435
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 45125
• # I/os (max): 364
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 45125
• Ram Bits: 3565158.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

1–66
Table 1–53. High-Speed I/O Specifications for Arria II GX Devices (Part 1 of 3)
Arria II Device Handbook Volume 3: Device Datasheet and Addendum
Clock
f
(input clock
frequency)–Row
I/O
f
(input clock
frequency)–
Column I/O
f
(output clock
frequency)–Row
I/O
f
(output clock
frequency)–
Column I/O
Transmitter
f
LVDS output data
rate)
HSCLK_IN
HSCLK_IN
HSCLK_OUT
HSCLK_OUT
HSDR_TX
Symbol
(true
Periphery Performance
1
SERDES factor,
Clock boost
Clock boost
Conditions
1 to 40
1 to 40
factor, W =
factor, W =
J = 3 to 10
dedicated
This section describes periphery performance, including high-speed I/O, external
memory interface, and IOE programmable delay.
I/O performance supports several system interfaces, for example the high-speed I/O
interface, external memory interface, and the PCI/PCI-X bus interface. I/O using
SSTL-18 Class I termination standard can achieve up to the stated DDR2 SDRAM
interfacing speed with typical DDR2 SDRAM memory interface setup. I/O using
general purpose I/O (GPIO) standards such as 3.0, 2.5, 1.8, or 1.5 LVTTL/LVCMOS
are capable of typical 200 MHz interfacing frequency with 10pF load.
Actual achievable frequency depends on design- and system-specific factors. You
should perform HSPICE/IBIS simulations based on your specific design and system
setup to determine the maximum achievable frequency in your system.
High-Speed I/O Specification
Table 1–53
SERDES)
(using
—
—
(1)
(1)
lists the high-speed I/O timing for Arria II GX devices.
Min
150
5
5
5
5
I3
1250
Max
670
500
670
500
(2)
Min
150
5
5
5
5
C4
1250
Max
670
500
670
500
(2)
Min
150
5
5
5
5
Chapter 1: Device Datasheet for Arria II Devices
C5,I5
472.5
472.5
1050
Max
622
622
(2)
December 2010 Altera Corporation
Min
150
5
5
5
5
Switching Characteristics
C6
472.5
472.5
Max
500
500
840
Mbps
MHz
MHz
MHz
MHz
Unit