EP3C55F484C7N Altera, EP3C55F484C7N Datasheet - Page 51

• Manufacturer Part Number: EP3C55F484C7N
• Description: IC CYCLONE III FPGA 55K 484FBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C55F484C7N

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2396160
• Number Of I /o: 327
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Cyclone III
• Number Of Logic Blocks/elements: 55856
• # I/os (max): 327
• Frequency (max): 437.5MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 55856
• Ram Bits: 2396160
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• No. Of Logic Blocks: 3491
• Family Type: Cyclone III
• No. Of I/o's: 327
• I/o Supply Voltage: 3.3V
• Operating Frequency Max: 437.5MHz
• Operating Temperature Range: 0°C To +85°C
• Rohs Compliant: Yes
• For Use With: 544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2509

Chapter 3: Memory Blocks in the Cyclone III Device Family
Clocking Modes
Clocking Modes
Independent Clock Mode
I/O Clock Mode
© December 2009
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Altera Corporation
Cyclone III device family M9K memory blocks support the following clocking modes:
■
■
■
■
When using read or write clock mode, if you perform a simultaneous read or write to
the same address location, the output read data is unknown. If you require the output
data to be a known value, use either single-clock mode or I/O clock mode and choose
the appropriate read-during-write behavior in the MegaWizard Plug-In Manager.
Violating the setup or hold time on the memory block input registers might corrupt
the memory contents. This applies to both read and write operations.
Asynchronous clears are available on read address registers, output registers, and
output latches only.
Table 3–5
Table 3–5. Cyclone III Device Family Memory Clock Modes
Cyclone III device family M9K memory blocks can implement independent clock
mode for true dual-port memories. In this mode, a separate clock is available for each
port (port A and port B). clock A controls all registers on the port A side, while
clock B controls all registers on the port B side. Each port also supports
independent clock enables for port A and B registers.
Cyclone III device family M9K memory blocks can implement input or output clock
mode for FIFO, single-port, true, and simple dual-port memories. In this mode, an
input clock controls all input registers to the memory block, including data, address,
byteena, wren, and rden registers. An output clock controls the data-output
registers. Each memory block port also supports independent clock enables for input
and output registers.
Independent
Input or output
Read or write
Single-clock
Clocking Mode
Independent
Input or output
Read or write
Single-clock
lists the clocking mode versus memory mode support matrix.
True Dual-Port
Mode
v
v
—
v
Dual-Port
Simple
Mode
v
v
v
—
Single-Port
Mode
—
v
—
v
Cyclone III Device Handbook, Volume 1
ROM Mode
v
v
v
—
FIFO Mode
v
v
—
—
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