EP3C55F484C7N Altera, EP3C55F484C7N Datasheet - Page 185

• Manufacturer Part Number: EP3C55F484C7N
• Description: IC CYCLONE III FPGA 55K 484FBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C55F484C7N

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2396160
• Number Of I /o: 327
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Cyclone III
• Number Of Logic Blocks/elements: 55856
• # I/os (max): 327
• Frequency (max): 437.5MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 55856
• Ram Bits: 2396160
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• No. Of Logic Blocks: 3491
• Family Type: Cyclone III
• No. Of I/o's: 327
• I/o Supply Voltage: 3.3V
• Operating Frequency Max: 437.5MHz
• Operating Temperature Range: 0°C To +85°C
• Rohs Compliant: Yes
• For Use With: 544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2509

Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family
Configuration Features
© December 2009
f
Altera Corporation
The AP configuration scheme in Cyclone III devices supports flash speed grades of
40 MHz and above. However, the AP configuration for all these speed grades must be
capped at 40 MHz. The advantage of faster speed grades is realized when your design
in the Cyclone III device accesses flash memory in user mode.
For more information about the operation of the Numonyx StrataFlash Embedded
Memory P30 and P33 flash memories, search for the keyword “P30” or “P33” on the
Numonyx website (www.numonyx.com) to obtain the P30 or P33 family data sheet.
Single-Device AP Configuration
The following groups of interface pins are supported in Numonyx P30 and P33 flash
memories:
■
■
■
Following are the control signals from the supported parallel flash memories:
■
■
■
■
■
■
The supported parallel flash memories output a control signal (WAIT) to Cyclone III
devices to indicate when synchronous data is ready on the data bus. Cyclone III
devices have a 24-bit address bus connecting to the address bus (A[24:1]) of the
flash memory. A 16-bit bidirectional data bus (DATA[15..0]) provides data transfer
between the Cyclone III device and the flash memory.
The following are the control signals from the Cyclone III device to flash memory:
■
■
■
■
■
■
Control pins
Address pins
Data pins
CLK
active-low reset (RST#)
active-low chip enable (CE#)
active-low output enable (OE#)
active-low address valid (ADV#)
active-low write enable (WE#)
DCLK
nRESET
FLASH_nCE
nOE
nAVD
nWE
Cyclone III Device Handbook, Volume 1
9–25