EP2SGX60EF1152C3N Altera, EP2SGX60EF1152C3N Datasheet - Page 7

• Manufacturer Part Number: EP2SGX60EF1152C3N
• Description: IC STRATIX II GX 60K 1152-FBGA
• Manufacturer: Altera
• Series: Stratix® II GXr

Specifications of EP2SGX60EF1152C3N

• Number Of Logic Elements/cells: 60440
• Number Of Labs/clbs: 3022
• Total Ram Bits: 2544192
• Number Of I /o: 534
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2181

Referenced
Document
Document
Revision History
Altera Corporation
October 2007
Date and Document
October 2007, v1.6
August 2007, v1.5
February 2007, v1.4
June 2006, v1.3
April 2006, v1.2
February 2006, v1.1
October 2005
v1.0
Table 1–4. Document Revision History
Version
Updated
Minor text edits.
Added “Referenced Documents” section.
Minor text edits.
●
●
●
Added the “Document Revision History”
section to this chapter.
●
●
●
●
Added chapter to the Stratix II GX Device
Handbook.
Changed 622 Mbps to 600 Mbps on
page 1-2 and Table 1–1.
Deleted “DC coupling” from the
Transceiver Block Features list.
Changed 4 to 6 in the PLLs row
(columns 3 and 4) of Table 1–1.
Updated Table 1–2.
Updated Table 1–1.
Updated Table 1–2.
Updated Table 1–1.
This chapter references the following document:
■
Table 1–4
Pitch (mm)
Area (mm
Length width (mm × mm)
“Features”
Table 1–3. Stratix II GX FineLine BGA Package Sizes
Stratix II GX Architecture
Device Handbook
Changes Made
Dimension
2
shows the revision history for this chapter.
)
section.
780 Pins
chapter in volume 1 of the Stratix II GX
29 × 29
1.00
841
Added support information for the
Stratix II GX device.
Updated numbers for receiver channels and
user I/O pin counts in Table 1–2.
Stratix II GX Device Handbook, Volume 1
Summary of Changes
1,152 Pins
35 × 35
1,225
1.00
1,508 Pins
Introduction
40 × 40
1,600
1.00
1–5