EP2SGX60EF1152C3N Altera, EP2SGX60EF1152C3N Datasheet - Page 67

• Manufacturer Part Number: EP2SGX60EF1152C3N
• Description: IC STRATIX II GX 60K 1152-FBGA
• Manufacturer: Altera
• Series: Stratix® II GXr

Specifications of EP2SGX60EF1152C3N

• Number Of Logic Elements/cells: 60440
• Number Of Labs/clbs: 3022
• Total Ram Bits: 2544192
• Number Of I /o: 534
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2181

Figure 2–43. ALM in Shared Arithmetic Mode
Note to
(1)
Altera Corporation
October 2007
Inputs dataf0 and dataf1 are available for register packing in shared arithmetic mode.
Figure
datae0
datae1
datab
dataa
datad
datac
2–43:
Adder trees are used in many different applications. For example, the
summation of the partial products in a logic-based multiplier can be
implemented in a tree structure. Another example is a correlator function
that can use a large adder tree to sum filtered data samples in a given time
frame to recover or to de-spread data which was transmitted utilizing
spread spectrum technology. An example of a three-bit add operation
utilizing the shared arithmetic mode is shown in
sum (S[2..0]) and the partial carry (C[2..0]) is obtained using the
LUTs, while the result (R[2..0]) is computed using the dedicated
adders.
4-Input
4-Input
4-Input
4-Input
LUT
LUT
LUT
LUT
shared_arith_out
shared_arith_in
carry_out
carry_in
Stratix II GX Device Handbook, Volume 1
D
D
reg0
reg1
Q
Q
Figure
Stratix II GX Architecture
To general or
To general or
To general or
To general or
local routing
local routing
local routing
local routing
2–44. The partial
2–59