EP2S15F672C3N Altera, EP2S15F672C3N Datasheet - Page 12

IC STRATIX II FPGA 15K 672-FBGA

EP2S15F672C3N

Manufacturer Part Number
EP2S15F672C3N
Description
IC STRATIX II FPGA 15K 672-FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet

Specifications of EP2S15F672C3N

Number Of Logic Elements/cells
15600
Number Of Labs/clbs
780
Total Ram Bits
419328
Number Of I /o
366
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
672-FBGA
No. Of Macrocells
15600
Family Type
Stratix II
No. Of I/o's
366
Clock Management
DLL, PLL
I/o Supply Voltage
3.6V
Operating Frequency Max
550MHz
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-1880
EP2S15F672C3N

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
EP2S15F672C3N
Manufacturer:
ALTERA
Quantity:
500
Part Number:
EP2S15F672C3N
Manufacturer:
Altera
Quantity:
10 000
Part Number:
EP2S15F672C3N
Manufacturer:
ALTERA
0
Logic Array Blocks
Figure 2–2. Stratix II LAB Structure
2–4
Stratix II Device Handbook, Volume 1
Direct link
interconnect from
adjacent block
Direct link
interconnect to
adjacent block
LAB Interconnects
The LAB local interconnect can drive ALMs in the same LAB. It is driven
by column and row interconnects and ALM outputs in the same LAB.
Neighboring LABs, M512 RAM blocks, M4K RAM blocks, M-RAM
blocks, or DSP blocks from the left and right can also drive an LAB's local
interconnect through the direct link connection. The direct link
connection feature minimizes the use of row and column interconnects,
providing higher performance and flexibility. Each ALM can drive
24 ALMs through fast local and direct link interconnects.
shows the direct link connection.
Local Interconnect
LAB
from Either Side by Columns & LABs,
Local Interconnect is Driven
& from Above by Rows
Row Interconnects of
Variable Speed & Length
ALMs
Column Interconnects of
Variable Speed & Length
Altera Corporation
Direct link
interconnect from
adjacent block
Direct link
interconnect to
adjacent block
Figure 2–3
May 2007

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