EP2S60F672I4N Altera, EP2S60F672I4N Datasheet - Page 149

• Manufacturer Part Number: EP2S60F672I4N
• Description: IC STRATIX II FPGA 60K 672-FBGA
• Manufacturer: Altera
• Series: Stratix® IIr

Specifications of EP2S60F672I4N

• Number Of Logic Elements/cells: 60440
• Number Of Labs/clbs: 3022
• Total Ram Bits: 2544192
• Number Of I /o: 492
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 672-FBGA
• For Use With: 544-1700 - DSP KIT W/STRATIX II EP2S60N544-1697 - NIOS II KIT W/STRATIX II EP2S60N
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-1916; EP2S60F672I4N

Altera Corporation
April 2011
V
V
(DC)
V
V
(AC)
V
ΔV
V
(AC)
V
V
V
V
V
V
V
V
Symbol
Symbol
Table 5–21. SSTL-2 Class I & II Differential Specifications
Table 5–22. 1.2-V HSTL Specifications
CCIO
SWING
X
SWING
ISO
OX
CCIO
R E F
IH
IL
IH
IL
OH
OL
ISO
(AC) AC differential input cross
(DC) Low-level DC input voltage
(AC) Low-level AC input voltage
(DC) High-level DC input voltage
(AC) High-level AC input voltage
Output supply voltage
DC differential input voltage
point voltage
AC differential input voltage
Input clock signal offset
voltage
Input clock signal offset
voltage variation
AC differential output cross
point voltage
Output supply voltage
Reference voltage
High-level output voltage
Low-level output voltage
Parameter
Parameter
Conditions
I
I
O H
O H
Conditions
= 8 mA
= –8 mA
(V
(V
0.48 × V
CCIO
CCIO
V
V
V
Minimum
Minimum
R E F
R E F
R E F
2.375
0.36
–0.15
0.7
–0.24
–0.15
/2) – 0.2
/2) – 0.2
1.14
+ 0.08
+ 0.15
+ 0.15
C C I O
Stratix II Device Handbook, Volume 1
0.50 × V
0.5 × V
Typical
Typical
2.500
±200
1.20
DC & Switching Characteristics
CCIO
C C I O
(V
(V
0.52 × V
V
V
V
V
V
V
Maximum
CCIO
CCIO
Maximum
C C I O
C C I O
C C I O
R E F
R E F
R E F
2.625
1.26
/2) + 0.2
/2) + 0.2
– 0.08
– 0.15
– 0.15
+ 0.15
+ 0.24
+ 0.15
C C I O
Unit
Unit
5–13
mV
V
V
V
V
V
V
V
V
V
V
V
V
V
V