EPF10K100ARI240-3 Altera, EPF10K100ARI240-3 Datasheet - Page 59

• Manufacturer Part Number: EPF10K100ARI240-3
• Description: IC FLEX 10KA FPGA 100K 240-RQFP
• Manufacturer: Altera
• Series: FLEX-10K®r

Specifications of EPF10K100ARI240-3

• Number Of Logic Elements/cells: 4992
• Number Of Labs/clbs: 624
• Total Ram Bits: 24576
• Number Of I /o: 189
• Number Of Gates: 158000
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 240-RQFP
• Family Name: FLEX 10KA
• Number Of Usable Gates: 100000
• Number Of Logic Blocks/elements: 4992
• # Registers: 1218
• # I/os (max): 189
• Frequency (max): 125MHz
• Process Technology: CMOS
• Operating Supply Voltage (typ): 3.3V
• Logic Cells: 4992
• Ram Bits: 24567
• Device System Gates: 158000
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: RQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 544-1251

Altera Corporation
t
t
t
t
t
t
t
t
t
t
t
t
LUT
CLUT
RLUT
PACKED
EN
CICO
CGEN
CGENR
CASC
C
CO
COMB
Table 32. LE Timing Microparameters (Part 1 of 2)
Symbol
LUT delay for data-in
LUT delay for carry-in
LUT delay for LE register feedback
Data-in to packed register delay
LE register enable delay
Carry-in to carry-out delay
Data-in to carry-out delay
LE register feedback to carry-out delay
Cascade-in to cascade-out delay
LE register control signal delay
LE register clock-to-output delay
Combinatorial delay
Figure 28. Synchronous Bidirectional Pin External Timing Model
Tables 32
parameters. These internal timing parameters are expressed as worst-case
values. Using hand calculations, these parameters can be used to estimate
design performance. However, before committing designs to silicon,
actual worst-case performance should be modeled using timing
simulation and analysis.
timing parameters.
FLEX 10K Embedded Programmable Logic Device Family Data Sheet
Dedicated
Clock
through
Parameter
36
describe the FLEX 10K device internal timing
Tables 37
Note (1)
Output Register
Input Register
OE Register
D
D
D
CLRN
CLRN
CLRN
PRN
PRN
PRN
through
Q
Q
Q
38
describe FLEX 10K external
t
OUTCOBIDIR
t
t
XZBIDIR
ZXBIDIR
t
t
INHBIDIR
INSUBIDIR
Bidirectional
Pin
Conditions
59