ADSP-21261SKSTZ150 Analog Devices Inc, ADSP-21261SKSTZ150 Datasheet - Page 9

• Manufacturer Part Number: ADSP-21261SKSTZ150
• Description: IC DSP 32BIT 150MHZ 144LQFP
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Fixed/Floating Pointr

Specifications of ADSP-21261SKSTZ150

• Interface: DAI, SPI
• Clock Rate: 150MHz
• Non-volatile Memory: ROM (384 kB)
• On-chip Ram: 128kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.20V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• No. Of Bits: 32 / 40
• Frequency: 150MHz
• Supply Voltage: 1.2V
• Embedded Interface Type: Serial
• Supply Voltage Range: 1.14V To 1.26V
• Operating Temperature Range: 0°C To +70°C
• Digital Ic: RoHS Compliant
• Device Core Size: 32/40Bit
• Architecture: Super Harvard
• Format: Floating Point
• Clock Freq (max): 150MHz
• Mips: 150
• Device Input Clock Speed: 150MHz
• Ram Size: 128KB
• Program Memory Size: 384KB
• Operating Supply Voltage (typ): 1.2/3.3V
• Operating Supply Voltage (min): 1.14/3.13V
• Operating Supply Voltage (max): 1.26/3.47V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Package: 144LQFP
• Numeric And Arithmetic Format: Floating-Point
• Maximum Speed: 150 MHz
• Device Million Instructions Per Second: 150 MIPS
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

tions. It also is used for downloading components from the
Web, dropping them into the application, and publishing com-
ponent archives from within VisualDSP++. VCSE supports
component implementation in C/C++ or assembly language.
Use the expert linker to visually manipulate the placement of
code and data on the embedded system. View memory utiliza-
tion in a color-coded graphical form, easily move code and data
to different areas of the DSP or external memory with a drag of
the mouse, and examine run-time stack and heap usage. The
expert linker is fully compatible with existing linker definition
file (LDF), allowing the developer to move between the graphi-
cal and textual environments.
In addition to the software and hardware development tools
available from Analog Devices, third parties provide a wide
range of tools supporting the SHARC processor family. Hard-
ware tools include SHARC processor PC plug-in cards. Third
party software tools include DSP libraries, real-time operating
systems, and block diagram design tools.
EVALUATION KIT
Analog Devices offers a range of EZ-KIT Lite
forms to use as a cost-effective method to learn more about
developing or prototyping applications with Analog Devices
processors, platforms, and software tools. Each EZ-KIT Lite
includes an evaluation board along with an evaluation suite of
the VisualDSP++ development and debugging environment
with the C/C++ compiler, assembler, and linker. Also included
are sample application programs, power supply, and a USB
cable. All evaluation versions of the software tools are limited
for use only with the EZ-KIT Lite product.
The USB controller on the EZ-KIT Lite board connects the
board to the USB port of the user’s PC, enabling the
VisualDSP++ evaluation suite to emulate the on-board proces-
sor in-circuit. This permits the customer to download, execute,
and debug programs for the EZ-KIT Lite system. It also allows
in-circuit programming of the on-board flash device to store
user-specific boot code, enabling the board to run as a standal-
one unit, without being connected to the PC.
With a full version of VisualDSP++ installed (sold separately),
engineers can develop software for the EZ-KIT Lite or any cus-
tom-defined system. Connecting one of Analog Devices JTAG
emulators to the EZ-KIT Lite board enables high speed, nonin-
trusive emulation.
DESIGNING AN EMULATOR-COMPATIBLE DSP
BOARD (TARGET)
The Analog Devices family of emulators are tools that every
DSP developer needs to test and debug hardware and software
systems. Analog Devices has supplied an IEEE 1149.1 JTAG test
access port (TAP) on each JTAG DSP. Nonintrusive in-circuit
emulation is assured by the use of the processor’s JTAG inter-
face—the emulator does not affect target system loading or
timing. The emulator uses the TAP to access the internal fea-
†
EZ-KIT Lite is a registered trademark of Analog Devices, Inc.
®†
evaluation plat-
Rev. F | Page 9 of 44 | July 2009
tures of the DSP, allowing the developer to load code, set
breakpoints, observe variables, observe memory, and examine
registers. The DSP must be halted to send data and commands,
but once an operation has been completed by the emulator, the
DSP system is set running at full speed with no impact on sys-
tem timing.
To use these emulators, the target board must include a header
that connects the DSP’s JTAG port to the emulator.
For details on target board design issues including mechanical
layout, single processor connections, multiprocessor scan
chains, signal buffering, signal termination, and emulator pod
logic, see the EE-68: Analog Devices JTAG Emulation Technical
Reference on the Analog Devices website (www.analog.com)—
use site search on “EE-68.” This document is updated regularly
to keep pace with improvements to emulator support.
ADDITIONAL INFORMATION
This data sheet provides a general overview of the ADSP-2126x
architecture and functionality. For detailed information on the
ADSP-2126x family core architecture and instruction set, refer
to the ADSP-2126x SHARC DSP Core Manual and the
ADSP-21160 SHARC DSP Instruction Set Reference.
ADSP-21261/ADSP-21262/ADSP-21266