ADSP-21261SKSTZ150 Analog Devices Inc, ADSP-21261SKSTZ150 Datasheet - Page 34

• Manufacturer Part Number: ADSP-21261SKSTZ150
• Description: IC DSP 32BIT 150MHZ 144LQFP
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Fixed/Floating Pointr

Specifications of ADSP-21261SKSTZ150

• Interface: DAI, SPI
• Clock Rate: 150MHz
• Non-volatile Memory: ROM (384 kB)
• On-chip Ram: 128kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.20V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• No. Of Bits: 32 / 40
• Frequency: 150MHz
• Supply Voltage: 1.2V
• Embedded Interface Type: Serial
• Supply Voltage Range: 1.14V To 1.26V
• Operating Temperature Range: 0°C To +70°C
• Digital Ic: RoHS Compliant
• Device Core Size: 32/40Bit
• Architecture: Super Harvard
• Format: Floating Point
• Clock Freq (max): 150MHz
• Mips: 150
• Device Input Clock Speed: 150MHz
• Ram Size: 128KB
• Program Memory Size: 384KB
• Operating Supply Voltage (typ): 1.2/3.3V
• Operating Supply Voltage (min): 1.14/3.13V
• Operating Supply Voltage (max): 1.26/3.47V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Package: 144LQFP
• Numeric And Arithmetic Format: Floating-Point
• Maximum Speed: 150 MHz
• Device Million Instructions Per Second: 150 MIPS
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADSP-21261/ADSP-21262/ADSP-21266
SPI Interface Protocol—Slave
Table 36. SPI Interface Protocol—Slave
Parameter
Timing Requirements
t
t
t
t
t
t
t
t
Switching Characteristics
t
t
t
t
t
SPICLKS
SPICHS
SPICLS
SDSCO
HDS
SSPIDS
HSPIDS
SDPPW
DSOE
DSDHI
DDSPIDS
HDSPIDS
DSOV
CPHASE = 1
CPHASE = 0
(OUTPUT)
(OUTPUT)
(CP = 0)
(CP = 1)
(INPUT)
(INPUT)
(INPUT)
SPICLK
(INPUT)
SPICLK
(INPUT)
SPIDS
MISO
MOSI
MISO
MOSI
t
S D S C O
t
t
t
D S O E
D S O E
D S O V
Serial Clock Cycle
Serial Clock High Period
Serial Clock Low Period
SPIDS Assertion to First SPICLK Edge
CPHASE = 0
CPHASE = 1
Last SPICLK Edge to SPIDS Not Asserted CPHASE = 0
Data Input Valid to SPICLK Edge (Data Input Setup Time)
SPICLK Last Sampling Edge to Data Input Not Valid
SPIDS Deassertion Pulse Width (CPHASE = 0)
SPIDS Assertion to Data Out Active
SPIDS Deassertion to Data High Impedance
SPICLK Edge to Data Out Valid (Data Out Delay Time)
SPICLK Edge to Data Out Not Valid (Data Out Hold Time)
SPIDS Assertion to Data Out Valid (CPHASE = 0)
t
t
S P IC H S
S S P I D S
t
t
D D S P I D S
MSB VALID
S P I C L S
MSB VALID
MSB
MSB
t
D D S P I D S
Figure 25. SPI Interface Protocol—Slave
t
Rev. F | Page 34 of 44 | July 2009
t
S P I C H S
S P I C L S
t
S S P I D S
t
D D S P I D S
LSB VALID
t
t
S P I C L K S
S S P I D S
t
H D S P I D S
LSB
LSB VALID
t
H S P I D S
t
H S P I D S
t
Min
4 × t
2 × t
2 × t
2 × t
2 × t
2 × t
2
2
2 × t
0
0
2 × t
H D S
LSB
CCLK
CCLK
CCLK
CCLK
CCLK
CCLK
CCLK
CCLK
– 2
– 2
+ 1
+ 1
– 2
t
S D P P W
t
t
t
D S D H I
H D S P I D S
D S D H I
Max
5
5
7.5
5 × t
CCLK
+ 2
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns