ADSP-21371KSWZ-2B Analog Devices Inc, ADSP-21371KSWZ-2B Datasheet - Page 36

• Manufacturer Part Number: ADSP-21371KSWZ-2B
• Description: IC DSP 32BIT 266MHZ 208-LQFP
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Floating Pointr

Specifications of ADSP-21371KSWZ-2B

• Package / Case: 208-LQFP
• Interface: DAI, DPI
• Operating Temperature: 0°C ~ 70°C
• Clock Rate: 266MHz
• Non-volatile Memory: ROM (512 kB)
• On-chip Ram: 128kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.20V
• Mounting Type: Surface Mount
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 21371
• Core Frequency Typ: 266MHz
• Dsp Type: Floating Point
• Mmac: 532
• No. Of Pins: 208
• Interface Type: SPI, UART
• Rohs Compliant: Yes
• Operating Temperature Range: 0°C To +70°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADSP-21371
S/PDIF Transmitter
Serial data input to the S/PDIF transmitter can be formatted as
left justified, I
20-, or 24-bits. The following sections provide timing for the
transmitter.
S/PDIF Transmitter-Serial Input Waveforms
Figure 24
left channel and low for the right channel. Data is valid on the
rising edge of SCLK. The MSB is delayed 12-bit clock periods
(in 20-bit output mode) or 16-bit clock periods (in 16-bit output
Figure 25
for the left channel and HI for the right channel. Data is valid on
the rising edge of SCLK. The MSB is left-justified to an LRCLK
transition but with a single SCLK period delay.
Figure 26
left channel and LO for the right channel. Data is valid on the
rising edge of SCLK. The MSB is left-justified to an LRCLK
transition with no MSB delay.
DAI_P20-1
DAI_P20-1
DAI_P20-1
DAI_P20-1
DAI_P20-1
DAI_P20-1
DAI_P20-1
DAI_P20-1
DAI_P20-1
LRCLK
SDATA
LRCLK
SDATA
LRCLK
SDATA
SCLK
SCLK
SCLK
shows the right-justified mode. LRCLK is high for the
shows the default I
shows the left-justified mode. LRCLK is high for the
2
S, or right justified with word widths of 16-, 18-,
LSB
MSB
MSB-1
MSB
MSB-1
MSB-2
2
S-justified mode. LRCLK is low
MS B-2
MSB
LS B+2
LEFT CHANNEL
LEFT CHANNEL
MSB-1
LS B+2 LSB+1
LSB+1
LEFT CHANNEL
MSB-2
LSB
Rev. 0 | Page 36 of 48 | June 2007
Figure 24. Right-Justified Mode
Figure 26. Left-Justified Mode
LSB
Figure 25. I
LSB+2 LSB+1
2
S-Justified Mode
LSB
MSB
mode) from an LRCLK transition, so that when there are 64
SCLK periods per LRCLK period, the LSB of the data will be
right-justified to the next LRCLK transition.
RIGHT CHANNEL
MSB-1
MSB
MSB-2
MS B-1
MS B-2
RIGHT CHANNEL
RIGHT CHANNEL
LSB+2
MSB
MSB-1
LSB +1
LSB+2
MSB-2
LS B+1
LSB
LSB
LSB+2
LSB+1
MSB
LSB
MSB+1
MSB