MT46H16M32LFCM-6 IT:B Micron Technology Inc, MT46H16M32LFCM-6 IT:B Datasheet - Page 95

• Manufacturer Part Number: MT46H16M32LFCM-6 IT:B
• Manufacturer: Micron Technology Inc
• Type: DDR SDRAMr

Specifications of MT46H16M32LFCM-6 IT:B

• Organization: 16Mx32
• Density: 512Mb
• Address Bus: 15b
• Access Time (max): 6.5/5ns
• Maximum Clock Rate: 166MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: VFBGA
• Operating Temp Range: -40C to 85C
• Operating Supply Voltage (max): 1.95V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 115mA
• Pin Count: 90
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Compliant

Clock Change Frequency
Figure 54: Clock Stop Mode
PDF: 09005aef82d5d305
512mb_ddr_mobile_sdram_t47m.pdf – Rev. I 12/09 EN
Command
DQ, DQS
Address
CK#
CKE
CK
Notes:
One method of controlling the power efficiency in applications is to throttle the clock
that controls the device. The clock can be controlled by changing the clock frequency or
stopping the clock.
The device enables the clock to change frequency during operation only if all timing
parameters are met and all refresh requirements are satisfied.
The clock can be stopped altogether if there are no DRAM operations in progress that
would be affected by this change. Any DRAM operation already in process must be com-
pleted before entering clock stop mode; this includes the following timings:
t
complete. (see READ Operation (page 60), and WRITE Operation (page 71).)
CKE must be held HIGH with CK = LOW and CK# = HIGH for the full duration of the
clock stop mode. One clock cycle and at least one NOP or DESELECT is required after
the clock is restarted before a valid command can be issued.
RFC,
Exit clock stop mode
1. Prior to Ta1, the device is in clock stop mode. To exit, at least one NOP is required be-
2. Any valid command is supported; device is not in clock suspend mode.
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fore issuing any valid command.
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MRD,
NOP
Ta1
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WR, and
CMD
t
Valid
Ta2
RPST. In addition, any READ or WRITE burst in progress must be
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95
512Mb: x16, x32 Mobile LPDDR SDRAM
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CMD
Tb3
Valid
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2
All DRAM activities must be complete
Tb4
NOP
Clock Change Frequency
Enter clock stop mode
© 2004 Micron Technology, Inc. All rights reserved.
NOP
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Don’t Care
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RCD,
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RP,