CYNCP80192-BGC Cypress Semiconductor Corp, CYNCP80192-BGC Datasheet - Page 11

• Manufacturer Part Number: CYNCP80192-BGC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYNCP80192-BGC

• Lead Free Status / Rohs Status: Not Compliant

Table 6-4. Error and Status Register
Table 6-5. Error Codes
Context Descriptor Index. This field identifies the context
descriptor that caused the last error condition. In the case of
multiple errors, this field will be overwritten.
DESC_AFULL. This bit indicates that the descriptor array is
almost full. When this flag is set, the processor(s) can send
only two more commands to the descriptors. The DESC_AF
flag will be cleared if more that two descriptors are available.
DESC_FULL. This bit indicates that the descriptor array is full.
When this flag is set, the processor can send no commands to
the descriptor. The DESC_FULL flag is cleared upon Reading
the status register.
SE_FULL.
SE. The SE bit indicates that the error is recoverable and that
the command has to be reissued.
Table 6-6. Information Register Description
7.0
There are 512 uniquely addressable 32-bit-wide registers (see
Table 7-1). These 512 registers are divided into 32 descriptors
and are called context descriptors (or “context”). Each context
comprises 16 registers (i.e., 32 × 16 = 512). Each of these
contexts is used for storing commands, data, and responses
(returned results from NSEs). These 32 contexts provide a 32-
Note:
Document #: 38-02043 Rev. *C
8.
ADR
Reserved
63–32
8
9
SE_FULL may be altered as a result of executing a Learn or Write command by the NSE. This flag will be cleared upon reading the status register.
Error Bit
Implementation
Operating Registers
[8]
Device ID
Revision
0
1
2
3
4
5
6
7
This bit indicates that the table in the NSE is full.
MFID
Field
HE
31
–
SE
30
Range
[31:16]
[63:32]
Invalid Command (SE)
Reserved
Reserved
Search or Learn size invalid (i.e., 11 in search size field is not allowed) (SE)
NSE access time out (HE)
Reserved
Reserved
Reserved
[15:8]
[6:4]
[3:0]
SE_FULL
7
29
1101_1100_0
Initial Value
00000011
111_1111
0001
001
0
–
DESC_FULL
28
Revision Number. This is the current device revision number. Numbers
start at one and increment by one for each revision of the device.
This is the CYNPC80192 implementation number.
Reserved.
Product code for CYNPC80192.
Manufacturer ID. This field is the same as the manufacturer ID used in the
TAP controller.
Reserved.
DESC_AFULL
HE. The HE bit indicates that the error is not recoverable, and
that the coprocessor has to be reset and reinitialized by the
software before further operations are attempted.
6.2.3
The mask register is 64 bits wide. The bits in this field can be
used to mask the INTR generated by any of the bits set in the
error and status register. Setting the bits in this register causes
the interrupt to be masked. The default value in the mask
register is FFFFFFFF (lower 32 bits only). The upper 32 bits of
the Mask Register [63:32] are reserved and cannot be written
to.
6.2.4
The information register is 64 bits wide. Table 6-6 describes
the lower-order 32 bits in the information register. It uses ADRs
8 and 9 of the CFG register area.
deep pipeline for the network processor(s) system. The
allocation of contexts between the multiple processors (or one
processor running multiple processors) can be done by the
network processor system. For example, a network processor
system having four processing elements can assign eight
contexts for each processor.
27
Error Description
Mask Register
Information Register
Reserved
26–13
Description
Context Desc Index
12–8
CYNCP80192
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Error Bits
7–0