CYNCP80192-BGC Cypress Semiconductor Corp, CYNCP80192-BGC Datasheet
CYNCP80192-BGC
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CYNCP80192-BGC Summary of contents
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... CYNCP80192 Network Database Coprocessor Cypress Semiconductor Corporation Document #: 38-02043 Rev. *C • 3901 North First Street • CYNCP80192 , San Jose CA 95134 • 408-943-2600 Revised November 29, 2004 ...
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... Context Descriptor Organization ...........................................................................................12 7.3 Context Descriptor Commands ............................................................................................. 13 8.0 NDC SUBSYSTEM POWER-UP INITIALIZATION PROCEDURE ................................................ 19 8.1 CYNCP80192 Reset Operation ................................................................................................................................ 19 9.0 NOBL PIPELINED SSRAM INTERFACE MODE .......................................................................... 19 10.0 NOBL FLOWTHROUGH SSRAM INTERFACE MODE .............................................................. 21 11.0 SYNCBURST PIPELINED SSRAM INTERFACE (EARLY WRITE) ............................................ 21 12.0 SYNCBURST PIPELINED SSRAM INTERFACE MODE (LATE WRITE) ................................... 23 13 ...
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... Figure 2-1. CYNCP80192 Block Diagram............................................................................................. 6 Figure 5-1. NDC Clocks ......................................................................................................................... 9 Figure 9-1. NoBL Pipelined SRAM Interface (Mode 000).................................................................. 20 Figure 10-1. NoBL Flow-through SSRAM Interface (Mode 001) ...................................................... 21 Figure 11-1. SyncBurst Pipelined SSRAM Interface (Early Write) .................................................. 22 Figure 12-1. SyncBurst Pipelined SSRAM Interface (Late Write) .................................................... 23 Figure 13-1. Configuration 1— ...
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... Table 16-2. Capacitance ..................................................................................................................... 26 Table 16-3. Operating Conditions ..................................................................................................... 27 Table 16-4. AC Timing Parameters for Pipelined NoBL SSRAM and SyncBurst SSRAM ............ 27 Table 16-5. AC Timing Parameters for NoBL and Flow-Through SSRAM ..................................... 27 Table 18-1. CYNPC80192 Pinout Description ................................................................................... 30 Table 19-1. Ordering Information ...................................................................................................... 34 Document #: 38-02043 Rev. *C LIST OF TABLES CYNCP80192 Page ...
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... This type of implementation is suited to applications where the associative data size eight bytes. • In the second system, the CYNCP80192 device returns the index of the successful search entry to the network processor. The network processor uses this index to access SSRAMs in order to get the required results ...
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... Conversion Controller Return ID Associative SSRAM Interface Figure 2-1. CYNCP80192 Block Diagram the commands to the NSE and steers the results to the appropriate locations in the operating registers. It also converts the SSRAM interface information from a network processor into protocol cycles of the NSE transactions. This ...
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... Signal Description Table 4-1 provides information on pins and signal names for the CYNCP80192 device. Under the “Type” heading Input Output, and T = three-state. Table 4-1. Search Coprocessor Pin Description Parameter Type Network Processor Interface IRST_L I Synchronous Reset Input. Active low. Initializes the device to a known state. ...
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... NoBL pipelined mode 001: NoBL flowthrough mode 010: SyncBurst pipelined mode (early Write) 011: SyncBurst pipelined mode (late Write) 100-111: Reserved. Note: 3. Detailed information on the external transceiver is given in ”Information on External Transceivers” on page 25. Document #: 38-02043 Rev. *C CYNCP80192 Description [3] . [3] [3] [3] [3] [3] ...
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... These registers are for configuring the NDC (Read/Write), reporting the error code in the status register (Read-only), setting up the mask register for asserting INTR (Read/Write), and obtaining information on the device (Read-only). R/W Dynamic access for searches and table management happens through this area of the coprocessor address space. CYNCP80192 Description [4] Page ...
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... The interrupt signal is programmable as active low or active high depending upon the system requirement. See the description of the CFG register for further detail. CYNCP80192 8 7–6 5–3 SSRAM ...
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... For example, a network processor system having four processing elements can assign eight contexts for each processor. CYNCP80192 26–13 12–8 Reserved Context Desc Index Mask Register ...
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... Reads the results from the context descriptor block (addresses 12–15 within the block). Note. In 64-bit bus mode, the even and the next odd location are accessed in the same cycle, and ADR[0] is ignored. Document #: 38-02043 Rev. *C CYNCP80192 Contents Context 0 Context 1 Context 2 Context 3 ...
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... Note. Learn command is not supported in the 272- bit wide table. The following describes the data that will be presented to the NSE for various search sizes. Data 0, layer attribute/valid bit for Data 0}) Data 2, layer attribute/valid bit for Data 2; layer attribute/valid bit for Data 0}. CYNCP80192 Access Context Descriptor Commands ...
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... The indices for SSR, GMR, and comparand register are stored in the command word also. (For further explanation of these indices, refer to data sheets for the CYNSE70XXX NSEs.) CYNCP80192 15–0 Address Pointer 15–0 Address Pointer ...
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... Writes into the NSEs. Note. The Move and Swap commands will not work across the NSE boundaries if several NSEs are cascaded. CYNCP80192 68-bit search: layer attribute and valid bits for Data 0. 136-bit search: layer attribute and valid bits for Data 272-bit search: layer attribute and valid bits for Data 23– ...
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... Reads are done from the NSE.) Result Register 1 contains the SE Data[67:4] Read from the NSE (Table 7-12) or Data[63:0] Read from the SSRAM connected to the NSE (Table 7-13). 63–0 SE Data[67:4] 63–0 SSRAM Data[63:0] CYNCP80192 18–16 15–0 Reserved Address[15:0] 18–16 15–0 Reserved ...
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... Done. This field indicates that the command has been processed. The done bit is cleared when the Result Register 0 is Read by the network processor. A new command can be initiated by the network processor through this descriptor after the done bit has cleared. Associative Data[63:0] 63–0 Associative Data[62:0] CYNCP80192 Reserved Reserved 3 2 ...
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... In the second method, the network processor uses the interrupt mechanism for Reading the command results. After the results are Ready in Result Registers 0 and 1 and the done bit is set, the NDC will assert pins CPID[7:0] (with the concatenated processor and context ID information) and CYNCP80192 Processor ID[4:0] ...
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... CLK2X) cycles, while the clock is running and both CYNCP80192 supplies are stable. In order to reset CYNSE70032/CYNSE70064A, IRST_L input to the CYNCP80192 needs to be asserted for at least (64 CLK2X) cycles, while the clock is running and both CYNCP80192 and CYNSE70032/CYNSE70064A voltage supplies are stable. Hardware Interface Timing Protocols—NDC Interface. The network processor interface of the NDC supports a variety of SSRAM interfaces ...
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... CLK ADR[9:0] A1 BW_L[7:0] DATA[63:0] CE_L CE_2 R/W_L STRB CPID[7:0] Write Figure 9-1. NoBL Pipelined SRAM Interface (Mode 000) Document #: 38-02043 Rev CPID Read Write Write CYNCP80192 Read Read Page ...
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... Read-cycle latency is one cycle, and there is no gap required between Read and Write operation. Every cycle is available for the network processor(s) for full utilization of the bus bandwidth. See Figure 11-1. Note. BWE_L is not used in this mode and should be tied inactive. CYNCP80192 ...
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... CLK ADR[9: BW_L[7:0] DATA[63:0] D1 CE_L CE_2 R/W_L STRB CPID[7:0] Write Read Figure 11-1. SyncBurst Pipelined SSRAM Interface (Early Write) Document #: 38-02043 Rev CPID NOP Write CYNCP80192 Read Page ...
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... Read and Write operation. Every cycle is available for the network processor(s) for full utilization of the bus bandwidth. See Figure 12-1. Note. BWE_L is not used in this mode and should be tied inactive CPID Read NOP Write CYNSE70XXX, and Coprocessor CYNCP80192 Read NSE SSRAM Bank Bank Page ...
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... SRAM interface can access the database coprocessing subsystem to implement a parallel packet processing system, as shown in Figure 13-3. Network Processors Network Processors Document #: 38-02043 Rev. *C Coprocessor SSRAM Bank Figure 13-2. Configuration 2—Index Mode Figure 13-3. Switching Systems Block Diagram CYNCP80192 NSE Bank Coprocessors SSRAMs Page ...
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... XVER_1_L XVER_2 XVER_2_L Figure 14-1. Use of Transceiver Enables provided in order to increase the ability of the signal to drive many transceiver devices of eight-bit width. Figure 14-2 shows one example of the distribution of signals driving the transceivers. Transceivers CYNCP80192 CYNCP80192 Transceivers Transceivers Transceivers NSEs SSRAM Page ...
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... Manufacturer ID. This field is the same as the manufacturer ID used in the TAP controller. Least Significant Bit. specifications, Test Conditions 0 < V < DDQ [9] 0 < V < V OUT DDQ 8 mA 3.3V DDQ 4 mA 3.3V DDQ [10] Description CYNCP80192 Description Min. Max. Unit –10 10 –10 10 0.4 2.4 TBD mA TBD mA Max. Unit [11] TBD pF [12] TBD ...
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... Hold time for ADR, CLK enable, data, Read/Write, CE, and byte Write enable. Document #: 38-02043 Rev. *C Min. 3.14 2.37 [13] 2.0 [14] –0.3 0 –5% Test Conditions Load (pF) [15] [15] [16] [17 Test Conditions is 3.3V supply). DDQ CYNCP80192 Max. Unit 3. °C +5% CYNPC80192–100 CYNPC80192–83 Min. Max. Min. 100 4.0 4.8 4 ...
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... Document #: 38-02043 Rev CYNCP80192 ...
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... SData 0 SData 3 SDATA6 SData SData SData SData SData DQ67 SData 2 SDATA5 SDATA8 SData SData SData SData DQ66 SData 1 SDATA4 SDATA7 SDATA9 SData SData SData CYNCP80192 DATA4 DATA4 DATA4 GND DATA4 GND DATA4 DATA4 DATA4 DATA4 DATA5 DATA4 DATA5 DATA5 DATA5 DATA5 ...
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... AC6 I/O AC7 I/O AC8 2.5 Volts AC9 I/O AE19 Output AE2 Output AE20 Output AE21 Output AE22 I/O AE23 CYNCP80192 Signal Name Signal Type DATA[12] I/O DATA[10] I/O V 2.5 Volts DD DQ[37] I/O DQ[39] I/O DQ[40] I/O DATA[08] I/O V 2.5 Volts ...
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... Input C16 Output C17 Output C18 I/O C19 Input C2 Output C20 Output C21 I/O C22 I/O C23 I/O C24 CYNCP80192 Signal Name Signal Type DQ[27] I/O DQ[30] I/O DQ[34] I/O CPID[0] Output CPID[2] Output IFC_CFG[0] Input CPID[5] Output TDI Input CPID[6] ...
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... Volts J23 3.3 Volts J24 I/O J25 I/O J26 2.5 Volts J3 I/O J4 I/O K1 I/O K2 I/O K23 2.5 Volts K24 CYNCP80192 Signal Name Signal Type SDATA[23] I/O SDATA[21] I/O V Ground SS DATA[46] I/O DATA[49] I/O DATA[52] I/O DATA[55] I/O DATA[58] I/O DATA[62] ...
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... R23 Ground R24 Ground R25 Ground R26 Ground R3 Ground R4 Ground T1 Input T11 Ground T12 I/O T13 I/O T14 CYNCP80192 Signal Name Signal Type SDATA[02] I/O SDATA[01] I/O ADR[9] Input V 3.3 Volts DDQ ADR[4] Input V 2.5 Volts DD V 2.5 Volts DD V Ground ...
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... V24 DQ[47] V25 DQ[49] V26 SSF V3 DATA[20 DDQ 19.0 Ordering Information Table 19-1 provides ordering CYNCP80192 device. Table 19-1. Ordering Information Part Number CYNPC80192-BGC Network Database Coprocessor Document #: 38-02043 Rev. *C Package Ball Signal Type Number I/O T15 Input T16 Ground T2 Input ...
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... In the following figures, the NDC package diagrams are shown from various views. Figure 20-1 shows the package from a bottom view, Figure 20-2 from a side view, and Figure 20-3 from a top view. Document #: 38-02043 Rev. *C Figure 20-1. Package Bottom View Figure 20-2. Package Side View CYNCP80192 Page ...
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... The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Figure 20-3. Package Top View CYNCP80192 Page ...
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... Orig. of Change AFX New data sheet FSG Typo in ordering information table (changed from CYNCP80192-100 to CYNCP80192-BGC) DCU Clarified scope and description of BIG/LTL_L signal Clarified SSRAM feature support Corrected timing diagram for SyncBurst SSRAM interface (early write) AOG Changed all occurances of ZBT to NoBL Changed IDT references to Cypress Changed ‘ ...