KU82596CA33 S N222 Intel, KU82596CA33 S N222 Datasheet
KU82596CA33 S N222
Specifications of KU82596CA33 S N222
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KU82596CA33 S N222 Summary of contents
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... Statistical Counters 82586 Software Compatible ✹ Self-Test Diagnostics ✹ Figure 1? 82596CA Block Diagram 82596CA Optimized CPU Interface ✹ — Optimized Bus Interface to Intel i486 DX, i486 SX, i487SX and TM TM 80960CA Processors — 33 MHz, 25 MHz, 20 MHz and 16 MHz Clock Frequencies — Supports Big Endian and Little ...
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... The Intel product(s) described in this document may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. ...
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High-Performance 32-Bit Local Area Network Coprocessor CONTENTS INTRODUCTION PIN DESCRIPTIONS 82596 AND HOST CPU INTERACTION 82596 BUS INTERFACE 82596 MEMORY ADDRESSING 82596 SYSTEM MEMORY STRUCTURE TRANSMIT AND RECEIVE MEMORY STRUCTURES TRANSMITTING FRAMES RECEIVING FRAMES 82596 NETWORK MANAGEMENT AND ...
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... INTRODUCTION The 82596CA is an intelligent high-performance 32-bit Local Area Network coprocessor 82596CA implements the CSMA CD access method and can be configured to support all existing IEEE 802 3 standards TYPEs 10BASE-T 10BASE2 1BASE5 and 10BROAD36 It can also be used to implement the proposed standard TYPE 10BASE-F The 82596CA performs high-level com- ...
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... The 82596CA is fabricated with Intel’s reliable 5-V CHMOS IV (process 648 8) technology It is available in a 132-pin PQFP or PGA package Figure 2 82596CA PQFP Pin Configuration 4 290218 – 2 ...
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Figure 3 82596CA PGA Pinout 82596CA 290218 – ...
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PGA Cross Reference by Pin Name Address Data Signal Pin No Signal Pin M10 P11 N11 P12 D5 D1 ...
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PIN DESCRIPTIONS PQFP Symbol Type Pin No CLK 9 I CLOCK The system clock input provides the fundamental timing for the 82596 CLK input used to generate the 82596 clock and requires TTL levels All external ...
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PIN DESCRIPTIONS (Continued) PQFP Symbol Type Pin No ADS 124 O ADDRESS STATUS The 82596 uses this tri-state pin to indicate to indicate that a valid bus cycle has begun and that A31 – A2 BE3 – BE0 and ...
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PIN DESCRIPTIONS (Continued) PQFP Symbol Type Pin No BS16 129 I BUS SIZE This signal allows the 82596CA to work with either 16- or 32-bit bytes Inserting BS16 low causes the 82596 to perform two 16- bit memory accesses when ...
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PIN DESCRIPTIONS (Continued) PQFP Symbol Type Pin Pins POWER Pins GROUND TxD 54 O TRANSMIT DATA This pin transmits data to the serial link It is high when not transmitting ...
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... A self-test can be used for board testing the 82596 will execute a self-test and write the re- sults to memory 82596 BUS INTERFACE The 82596CA has bus interface timings and pin defi- nitions that are compatible with Intel’s 32-bit i486 TM SX and i486 TM DX microprocessors eliminates the need for additional bus interface logic Operating at 33 MHz the 82596’ ...
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Figure 4 82596 and Host CPU Intervention Table 1 82596 Memory Addressing Formats Pointer or Offset ISCP Address 24-Bit Linear SCB Address Base (24) Command Block Pointers Base (24) Rx Frame Descriptors Base (24) Tx Frame Descriptors Base (24) ...
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Figure 6 82596 Shared Memory Structure 82596 SYSTEM MEMORY STRUCTURE The Shared Memory structure consists of four parts the Initialization Root the System Control Block the Command List and the Receive Frame Area (see Figure 6) The Initialization Root is ...
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Ready Suspended No Receive Resources etc ) in- terrupt bits (Command Completed Frame Received CU Not Ready and RU Not Ready) and statistical counters The Command List functions as a program for the CU individual commands are placed in ...
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Figure 7 Frame Reception in the RFA 82596CA 290218 –7 15 ...
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Figure 8 Simplified Memory Structure Figure 9 Flexible Memory Structure 16 290218 – 8 290218 – 9 ...
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TRANSMITTING FRAMES The 82596 executes high-level Action Commands from the Command List in system memory Action Commands are fetched and executed in parallel with the host CPU operation thereby significantly improv- ing system performance The format of the Action Commands ...
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RECEIVING FRAMES To reduce CPU overhead the 82596 is designed to receive frames without CPU supervision The host CPU first sets aside an adequate receive buffer space and then enables the 82596 Receive Unit Once enabled the RU watches ...
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Figure 13 Receive Frame Area Diagram Figure 14 Receive Frame Descriptor 82596CA 290218 –12 290218 –13 19 ...
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NETWORK PLANNING AND MAINTENANCE To properly plan operate and maintain a communi- cation network the network management entity must accumulate information on network behavior The 82596 provides a rich set of network-wide diag- nostics that can serve as the ...
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STATION DIAGNOSTICS AND SELF-TEST The 82596 provides a large set of diagnostic and network management functions These include inter- nal and external loopback and time domain reflec- tometry for locating fault points in the network cable The 82596 ensures software ...
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The following diagram illustrates the format of the SCP 31 ODD WORD SYSBUS ...
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INTERMEDIATE SYSTEM CONFIGURATION POINTER (ISCP) The ISCP indicates the location of the System Control Block Often the SCP is in ROM and the ISCP is in RAM The CPU loads the SCB address (or an equivalent data structure) into the ...
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CONTROLLING THE 82596CA The host CPU controls the 82596 with the commands data structures and methods described in this section The CPU and the 82596 communicate through shared memory structures The 82596 contains two indepen- dent units the Command ...
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Mode A Linear address is a single 24-bit entity Address pins A A Segmented address uses a 24-bit base and a 16-bit offset 32-bit Segmented Mode A Linear address is a single 32-bit entity A Segmented address uses a ...
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COMMAND UNIT (CU) The Command Unit is the logical unit that executes Action Commands from a list of commands very similar to a CPU program A Command Block is associated with each Action Command The CU is modeled as ...
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SYSTEM CONTROL BLOCK (SCB) The SCB is a memory block that plays a major role in communications between the CPU and the 82596 Such communications include the following Commands issued by the CPU Status reported by the 82596 Control commands ...
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Events can be cleared only by CPU acknowledgment If some events are not acknowledged by the ACK field the Interrupt signal (INT) will be reissued after Channel Attention (CA) is processed Furthermore if a new event occurs while an ...
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Command Word 31 ACK 0 CUC These bits specify the action to be performed as a result This word is set by the CPU and cleared by the 82596 Defined bits are Bit 31 ACK-CX Acknowledges that ...
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Status Word 15 STAT 0 82586 mode 15 STAT 0 32-Bit Segmented and Linear mode Indicates the status of the 82596 This word is modified only by the 82596 Defined bits are Bit 15 CX The CU finished executing ...
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SCB STATISTICAL COUNTERS Statistical Counter Operation The CPU is responsible for clearing all error counters before initializing the 82596 The 82596 updates these counters by reading them adding 1 and then writing them back to the SCB The counters are ...
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OVRNERRS This 32-bit quantity contains the number of frames known to be lost because the local system bus was not available If the traffic problem lasts longer than the duration of one frame the frames that follow the first ...
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NOP This command results in no action by the 82596 except for those performed in the normal command process- ing It is used to manipulate the CBL manipulation The format of the NOP command is shown in Figure 21 NOP ...
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The format of the Individual Address Setup command is shown in Figure 22 IA Setup 82586 and 32-Bit Segmented Modes 31 ODD WORD INDIVIDUAL ADDRESS 6th ...
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The format of the Configure command is shown in Figure 23 24 and 25 31 ODD WORD Byte 1 Byte 0 Byte 5 Byte 4 Byte ...
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The P bit is valid only in the new memory structure modes In 82586 mode this bit is disabled ( prefetched mark) 7 MONITOR X BYTE 1 FIFO Limit (Bits 0– 3) FIFO limit MONITOR (Bits 6– ...
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BYTE 6 SLOT TIME (L) Slot time low byte DEFAULT 00h 7 MAXIMUM RETRY NUMBER BYTE 7 SLOT TIME (H) Slot time high part (Bits 0–2) RETRY NUM (Bits 4– 7) Number of transmission retries on collision DEFAULT F2h ...
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BYTE 10 MIN FRAME LEN Minimum frame length DEFAULT 40h 7 MONITOR MC ALL BYTE 11 PRECRS (Bit 0) Preamble until Carrier Sense LNGFLD (Bit 1) Length field Enables padding at the End-of-Carrier framing (802 3) CRCINM (Bit ...
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A reset (hardware or software) configures the 82596 according to the following defaults Parameter ADDRESS LENGTH A L FIELD LOCATION AUTO RETRANSMIT BITSTUFFING EOC BROADCAST DISABLE CDBSAC CDT FILTER CDT SRC CRC IN MEMORY CRC-16 CRC-32 CRS FILTER CRS SRC ...
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Multicast-Setup This command is used to load the 82596 with the Multicast-IDs that should be accepted As noted previously the filtering done on the Multicast-IDs is not perfect and some unwanted frames may be accepted This command resets the ...
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Transmit This command is used to transmit a frame of user data onto the serial link The format of a Transmit command is as follows 31 ODD WORD ...
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per standard Command Block (see the NOP command for details) OK (Bit 13) Error free completion A (Bit 12) Indicates that the command was abnormally terminated due to CU Abort control command ...
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The interpretation of what is transmitted depends on the No Source Address insertion configuration bit and the memory model being used NOTES 1 The Destination Address and the Length Field are sequential The Length Field immediately follows the most significant ...
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EOF This bit indicates that this TBD is the last one associated with the frame being transmitted It is set by the CPU before transmit SIZE (ACT COUNT) This 14-bit quantity specifies the number of bytes that hold ...
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The format of the Time Domain Reflectometer command is 82586 and 32-Bit Segmented Modes 31 ODD WORD ...
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DUMP This command causes the contents of various 82596 registers to be placed in a memory area specified by the user It is supplied as a 82596 self-diagnostic tool and to provide registers of interest to the user The ...
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DMA CONTROL REGISTER CONFIGURE BYTES 3 2 CONFIGURE BYTES 5 4 CONFIGURE BYTES 7 6 CONFIGURE BYTES 9 8 CONFIGURE BYTES BYTES ...
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CONFIGURE BYTES CONFIGURE BYTES CONFIGURE BYTES BYTES BYTES CRC BYTES 0 1 LAST T ...
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Diagnose The Diagnose Command triggers an internal self-test procedure that checks internal 82596 hardware which includes Exponential Backoff Random Number Generator (Linear Feedback Shift Register) Exponential Backoff Timeout Counter Slot Time Period Counter Collision Number Counter Exponential Backoff Shift Register ...
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RECEIVE FRAME DESCRIPTOR Each received frame is described by one Receive Frame Descriptor (see Figure 37) Two new memory structures are available for the received frames The structures are available only in the Linear and 32-bit Segmented modes Simplified ...
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Note that this sequence is very useful for monitoring If the 82596 is configured to Save Bad Frames to receive in Promiscuous mode and to use the Simplified memory structure any programmed length of received data can be saved in ...
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Figure 39 RFA Flexible Memory Structure Buffers on the receive side can be different lengths The 82596 will not place more bytes into a buffer than indicated in the associated RBD The 82596 will fetch the next RBD before ...
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ODD WORD A15 RBD OFFSET 4th byte SOURCE ADDRESS 6th byte ...
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EL When set this bit indicates that this RFD is the last one on the RDL S When set this bit suspends the RU after receiving the frame SF This bit selects between the Simplified or the Flexible ...
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NOTES 1 The Destination address Source address and Length fields are packed i e one field immediately follows the next 2 The affect of Address Length Location (No Source Address Insertion) configuration parameter while re- ceiving is as follows 82586 ...
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EOF Indicates that this is the last buffer related to the frame It is cleared by the CPU before starting the RU and is written by the 82596 at the end of reception of the frame F Indicates ...
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PGA PACKAGE THERMAL SPECIFICATION Parameter Thermal Resistance ELECTRICAL AND TIMING CHARACTERISTICS Absolute Maximum Ratings Storage Temperature Case Temperature under Bias Supply Voltage with Respect ...
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... PORT Hold Time T31 BOFF Setup Time T32 BOFF Hold Time Timings shown are for the 82596CA C-Stepping For information regarding timings for the 82596CA A1 or B-Step contact your local Intel representative 58 on all outputs unless otherwise L 16 MHz Notes Min ...
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... PORT Hold Time T31 BOFF Setup Time T32 BOFF Hold Time Timings shown are for the 82596CA C-Stepping For information regarding timings for the 82596CA A1 or B-Step contact your local Intel representative 82596CA on all outputs unless otherwise L 20 MHz Notes Min ...
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... RESET Setup Time T24 RESET Hold Time T25 INT INT Valid Delay Timings shown are for the 82596CA C-Stepping For information regarding timings for the 82596CA A1 or B-Step contact your local Intel representative 60 on all outputs unless otherwise L 25 MHz Notes ...
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... PORT Hold Time T31 BOFF Setup Time T32 BOFF Hold Time Timings shown are for the 82596CA C-Stepping For information regarding timings for the 82596CA A1 or B-Step contact your local Intel representative 82596CA on all outputs unless otherwise L 25 MHz Notes Min ...
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... AHOLD Setup Time T21a HLDA Setup Time T22 AHOLD Hold Time Timings shown are for the 82596CA C-Stepping For information regarding timings for the 82596CA A1 or B-Step contact your local Intel representative 62 on all outputs unless otherwise L 33 MHz Notes Min ...
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... This calculation only provides a rough estimate for derating the frequency For more detailed information contact your Intel Sales Office for the data sheet supplement 3 CA pulse width need only wide if the set up and hold times are met BREQ must meet setup and hold times and ...
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TRANSMIT RECEIVE CLOCK PARAMETERS (Continued) Symbol Parameter RTS AND CTS PARAMETERS T49 TxC Low to RTS Low Time to Activate RTS T50 CTS Low to TxC Low CTS Setup Time T51 TxC Low to CTS Invalid CTS Hold Time ...
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TRANSMIT RECEIVE CLOCK PARAMETERS (Continued) Symbol Parameter INTERFRAME SPACING PARAMETERS T71 Interframe Delay EXTERNAL LOOPBACK-PIN PARAMETERS T72 TXC Low to LPBK Low T73 TXC Low to LPBK High NOTES 1 Special MOS levels and V e CIL ...
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BUS OPERATION The following figures show the 82596CA basic bus cycle and basic burst cycle Please refer to the 32-Bit LAN Component User’s Manual Figure 44 Basic 82596CA Bus Cycle Figure 45 Basic 82596CA Burst Cycle 66 290218 ...
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SYSTEM INTERFACE A C TIMING CHARACTERISTICS The measurements should be done testing inputs are driven for a logic ‘‘1’’ and ...
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INPUT WAVEFORMS Figure 48 CA and BREQ Input Timing Figure 49 INT INT Output Timing Figure 50 HOLD HLDA Timings Figure 51 Input Setup and Hold Time 68 290218 –21 290218 –22 290218 –23 290218 –24 ...
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Figure 52 Output Valid Delay Timing Figure 53 Output Float Delay Timing Figure 54 PORT Setup and Hold Time 82596CA 290218 –25 290218 –26 290218 –27 69 ...
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SERIAL AC TIMING CHARACTERISTICS Figure 56 Serial Input Clock Timing Figure 57 Transmit Data Waveforms 70 290218 –28 Figure 55 RESET Input Timing 290218 –29 290218 –30 ...
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Figure 58 Transmit Data Waveforms Figure 59 Receive Data Waveforms (NRZ) Figure 60 Receive Data Waveforms (CRS) 82596CA 290218 –31 290218 –32 290218 –33 71 ...
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... OUTLINE DIAGRAMS 132 LEAD CERAMIC PIN GRID ARRAY PACKAGE INTEL TYPE A Family Ceramic Pin Grid Array Package Millimeters Symbol Min Max 132 ISSUE IWS Inches Notes Min Max 0 140 0 180 Solid Lid 0 030 0 050 Solid Lid 0 105 0 135 0 045 0 055 ...
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... D1 E1 Package Body Bumper Distance Lead Dimension 10 16 REF D4 E4 Foot Radius Location Foot Length Issue IWS Preliminary Intel Case Outline Drawings Plastic Quad Flat Pack (PQFP) 0 025 Inch (0 635mm) Pitch Max Min Max Min Max Min 84 100 132 0 500 REF ...
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Figure 61 Principal Dimensions and Datums mm (inch) 74 Figure 62 Molded Details 290218 –35 290218 –36 ...
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Figure 63 Terminal Details mm (inch) Detail J Detail L Figure 64 Typical Lead 82596CA 290218 –37 290218 –38 75 ...
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REVISION SUMMARY The following represents the key differences be- tween version 004 and version 005 of the 82596CA Data Sheet 1 Timings added for -16 MHz and -20 MHz specfi- cations The following represents the key differences ...