FCD4B14CU Atmel, FCD4B14CU Datasheet - Page 16

• Manufacturer Part Number: FCD4B14CU
• Manufacturer: Atmel

Specifications of FCD4B14CU

• Lead Free Status / Rohs Status: Compliant

Power Management
Nap Mode
Static Current
Consumption
Dynamic Current
Consumption
Temperature
Stabilization Power
Consumption (TPP pin)
16
FCD4B14
Several strategies are possible to reduce power consumption when not in use.
The simplest and most efficient is to cut the power supply, using external means.
A nap mode is also implemented in the FCD4B14. To activate this nap mode, user must:
1. Set the reset RST pin to high. Doing this, all analog sections of the device are
2. Set the clock PCLK pin to high (or low), thus stopping the entire digital section.
3. Set the TPE pin to low or disconnect TPP to stop the temperature stabilization
4. Set Output Enable OE pin to high, so that output are forced in HiZ.
Figure 12. Nap Mode
In Nap Mode, all internal transistors are in shut mode. Only leakage current is drained in
power supply, generally less than the tested value.
When the clock is stopped (set to 1) and the reset is low (set to 0), the analog sections
of the device drain some current and the digital section does not consume current if the
outputs are connected to a standard CMOS input (= no current is drained in the I/O). In
this case the typical current value is 5 mA. This current does not depend on the voltage
(i.e. it is almost the same from 3V to 5.5V).
When the clock is running, the digital sections are consuming current, and particularly
the outputs if they are heavily loaded. In any case, it should be less than the testing
machine (120 pF load on each I/O), 50 pF maximum is recommended.
Connected to a USB interface chip (see application note 26 related to the FCDEMO4
kit) at 5V, and running at about 1 MHz, the FCD4B14 consumes less than 7 mA on VCC
pin.
When the TPE pin is set to 1, current is drained via the TPP pin. The current is limited by
the internal equivalent resistance given in table 4 and a possible external resistor.
Most of the time, TPE is set to 0 and no current is drained in TPP. When the image con-
trast becomes low because of a low temperature differential (less than one Kelvin), then
it is recommended to set TPE to 1 during a short time so that the dissipated power in the
chip elevates the temperature, enabling to recover contrast. The necessary time to
increase the chip temperature of one Kelvin depends on the dissipated power, the ther-
mal capacity of the silicon sensor and the thermal resistance between the sensor and
the surroundings.
As a rule of thumb, dissipating 300 mW in the chip elevates the temperature of 1 Kelvin
in one second. With the 30 Ω typical value, 300 mW is 3V applied on TPP.
internally powered down.
feature.
Clock PCLK
Reset RST
Nap mode
Nap
1962C–01/02