FCD4B14CU Atmel, FCD4B14CU Datasheet - Page 12

• Manufacturer Part Number: FCD4B14CU
• Manufacturer: Atmel

Specifications of FCD4B14CU

• Lead Free Status / Rohs Status: Compliant

Analog-to-Digital
Converter/
Reconstructing an 8-bit
Fingerprint Image
Start Sequence
Figure 8. Start Sequence
Reading the Frames
Read One Byte/Output
Enable
Power Supply Noise
Video Output
12
Clock PCLK
FCD4B14
Reset RST
An Analog-to-Digital Converter (ADC) is used to convert the analog signal coming from
the pixel into digital data that can be used by a processor.
As the data rate for parallel port and USB is in the range of 1 MB per second and at least
a rate of 500 frames per second is needed to reconstruct the image with a fair sweeping
speed for the finger, two 4-bit ADCs have been used to output 2 pixels at a time on 1
byte.
A reset is not necessary between each frame acquisition!
Start sequence must consist of:
1. Set the RST pin to high
2. Set the RST pin to low
3. Send 4 clock pulses (due to pipe-line)
4. Send clock pulses to skip the first frame
Note that the first frame never contains relevant information because the integration
time is not correct.
A frame consists of 280 true columns + 1 dummy column of 8 pixels. As two pixels are
output at a time, a system must send 281x4 = 1124 clock pulses to read one frame.
Reset must be low when reading the frames.
Clock is taken into account on the falling edge and data are output on the rising edge.
For each clock pulse, after the start sequence, a new byte is output on the Do0-3, De0-
3 pins. This byte contains 2 pixels: 4-bit on Do0-3 (odd pixels), 4-bit on De0-3 (even
pixels).
To output the data, the output enable (OE) pin must be low. When OE is high, the Do0-
3 and De0-3 pins are in high impedance state. This enables an easy connection to a
microprocessor bus without additional circuitry-it will enable data output by using a chip
select signal. Note that the FCD4B14 is always sending data: there is no data exchange
to perform using read/write mode.
IMPORTANT: When a falling edge is applied on OE (i.e when the Output Enable
becomes active), then some current is drained from the power supply to drive the 8 out-
puts, producing some noise. It is important to avoid such noise just after the falling edge
of the clock PCLK, when the pixels information is evaluated: the timing diagram figure 5
and time T
possible.
An analog signal is also available on pins AVE and AVO. Note that video output is avail-
able one clock pulse before the corresponding digital output (one clock pipe-line delay
for the analog to digital conversion).
NOOE
1
defines the interval time where the power supply must be as quiet as
2
4+1124 clock pulses to skip the first frame
3
4
1
1124
1
1962C–01/02