MT46V64M8P-75 Micron Technology Inc, MT46V64M8P-75 Datasheet - Page 75
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MT46V64M8P-75
Manufacturer Part Number
MT46V64M8P-75
Description
Manufacturer
Micron Technology Inc
Datasheet
1.MT46V64M8P-75.pdf
(91 pages)
Specifications of MT46V64M8P-75
Lead Free Status / Rohs Status
Compliant
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Figure 39:
PDF: 09005aef80a1d9d4/Source: 09005aef82a95a3a
DDR_x4x8x16_Core2.fm - 512Mb DDR: Rev. N; Core DDR Rev. B 2/09 EN
t DQSS (NOM)
Command
Consecutive WRITE-to-WRITE
Address
DQS
CK#
DM
Notes:
DQ
CK
WRITE
Bank,
1. DI b (or n) = data-in from column b (or column n).
2. Three subsequent elements of data-in are applied in the programmed order following DI b.
3. Three subsequent elements of data-in are applied in the programmed order following DI n.
4. An uninterrupted burst of 4 is shown.
5. Each WRITE command may be to any bank.
Col b
T0
t DQSS
NOP
DI
T1
b
T1n
WRITE
Bank,
Col n
T2
75
T2n
Micron Technology, Inc., reserves the right to change products or specifications without notice.
NOP
T3
DI
n
T3n
Transitioning Data
512Mb: x4, x8, x16 DDR SDRAM
NOP
T4
T4n
©2000 Micron Technology, Inc. All rights reserved.
T5
NOP
Don’t Care
Operations
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