MT8HTF12864HDZ-667H1 Micron Technology Inc, MT8HTF12864HDZ-667H1 Datasheet - Page 10

• Manufacturer Part Number: MT8HTF12864HDZ-667H1
• Description: MODULE DDR2 SDRAM 1GB 200SODIMM
• Manufacturer: Micron Technology Inc
• Series: -r

Specifications of MT8HTF12864HDZ-667H1

• Main Category: DRAM Module
• Sub-category: DDR2 SDRAM
• Module Type: 200SODIMM
• Device Core Size: 64b
• Organization: 128Mx64
• Total Density: 1GByte
• Chip Density: 1Mb
• Maximum Clock Rate: 667MHz
• Operating Supply Voltage (typ): 1.8V
• Operating Current: 908mA
• Number Of Elements: 8
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 200
• Mounting: Socket
• Memory Type: DDR2 SDRAM
• Memory Size: 1GB
• Speed: 667MT/s
• Features: -
• Package / Case: 200-SODIMM
• Lead Free Status / Rohs Status: Compliant

I
Table 8: DDR2 I
Values shown for MT47H64M16 DDR2 SDRAM only and are computed from values specified in the 1Gb (64 Meg x 16) com-
ponent data sheet
PDF: 09005aef831ec770
htf8c128x64hdz.pdf - Rev. C 3/10 EN
Parameter
Operating one bank active-precharge current:
t
inputs are switching; Data bus inputs are switching
Operating one bank active-read-precharge current: I
(I
CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching;
Data pattern is same as I
Precharge power-down current: All device banks idle;
Other control and address bus inputs are stable; Data bus inputs are floating
Precharge quiet standby current: All device banks idle;
HIGH, S# is HIGH; Other control and address bus inputs are stable; Data bus inputs
are floating
Precharge standby current: All device banks idle;
HIGH; Other control and address bus inputs are switching; Data bus inputs are switch-
ing
Active power-down current: All device banks open;
(I
Data bus inputs are floating
Active standby current: All device banks open;
(I
and address bus inputs are switching; Data bus inputs are switching
Operating burst write current: All device banks open; Continuous burst writes; BL
= 4, CL = CL (I
HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data
bus inputs are switching
Operating burst read current: All device banks open; Continuous burst read, I
= 0mA; BL = 4, CL = CL (I
(I
ing; Data bus inputs are switching
Burst refresh current:
val; CKE is HIGH, S# is HIGH between valid commands; Other control and address bus
inputs are switching; Data bus inputs are switching
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and address bus
inputs are floating; Data bus inputs are floating
DD
RAS =
DD
DD
DD
DD
), AL = 0;
); CKE is LOW; Other control and address bus inputs are stable;
),
); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switch-
Specifications
t
RP =
t
RAS MIN (I
t
RP (I
t
DD
CK =
), AL = 0;
DD
DD
DD
); CKE is HIGH, S# is HIGH between valid commands; Other control
t
CK (I
); CKE is HIGH, S# is HIGH between valid commands; Address bus
Specifications and Conditions – 1GB (Die Revision E)
t
DD
DD
DD4W
CK =
t
CK =
),
), AL = 0;
t
RC =
t
CK (I
t
CK (I
t
RC (I
DD
t
DD
CK =
); REFRESH command at every
),
DD
t
RAS =
),
t
CK (I
t
RAS =
DD
t
RAS MAX (I
),
t
CK =
t
t
RAS MIN (I
t
CK =
RAS =
t
CK =
t
CK =
t
CK (I
t
CK (I
t
OUT
CK =
t
t
t
CK (I
RAS MAX (I
CK =
DD
10
t
DD
CK
= 0mA; BL = 4, CL = CL
DD
),
DD
),
t
DD
t
),
CK (I
),
RP =
t
t
CK (I
); CKE is HIGH, S# is
RAS =
t
t
RCD =
RC =
t
1GB (x64, DR) 200-Pin DDR2 SODIMM
RFC (I
DD
Fast PDN exit
MR[12] = 0
Slow PDN exit
MR[12] = 1
t
DD
Micron Technology, Inc. reserves the right to change products or specifications without notice.
RP (I
DD
); CKE is LOW;
t
t
); CKE is
RC (I
RAS MAX
),
t
RCD (I
DD
DD
t
RP =
) inter-
); CKE is
DD
),
DD
t
OUT
RP
);
Symbol
I
I
I
I
I
I
I
DD4W
DD2Q
I
I
DD2N
DD3N
DD4R
I
I
DD2P
DD3P
DD0
DD1
DD5
DD6
1
1
2
2
2
2
1
2
2
2
1
© 2008 Micron Technology, Inc. All rights reserved.
I
DD
-800
1288
1308
2240
628
728
600
640
320
680
56
80
56
Specifications
2160
-667
568
548
520
560
240
600
828
908
56
80
56
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA