PI7C8150ND Pericom Semiconductor, PI7C8150ND Datasheet - Page 88

• Manufacturer Part Number: PI7C8150ND
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8150ND

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 85C
• Package Type: BGA
• Rad Hardened: No
• Case: BGA
• Dc: 04+
• Lead Free Status / Rohs Status: Not Compliant

14.1.42
PORT OPTION REGISTER – OFFSET 74h
Bit
0
1
2
3
4
8:5
9
10
Function
Reserved
Primary MEMR
Command Alias
Enable
Primary MEMW
Command Alias
Enable
Secondary
MEMR
Command Alias
Enable
Secondary
MEMW
Command Alias
Enable
Reserved
Enable Long
Request
Enable
Secondary To
Hold Request
Longer
Type
R/O
R/W
R/W
R/W
R/W
R/O
R/W
R/W
Description
Reserved. Returns 0 when read. Reset to 0.
Controls PI7C8150’s detection mechanism for matching memory
read retry cycles from the initiator on the primary interface
0: exact matching for non-posted memory write retry cycles from
initiator on the primary interface
1: alias MEMRL or MEMRM to MEMR for memory read retry
cycles from the initiator on the primary interface
Reset to 0
Controls PI7C8150’s detection mechanism for matching non-posted
memory write retry cycles from the initiator on the primary interface
0: exact matching for non-posted memory write retry cycles from
initiator on the primary interface
1: alias MEMWI to MEMW for non-posted memory write retry
cycles from initiator on the primary interface
Reset to 0
Controls PI7C8150’s detection mechanism for matching memory
read retry cycles from the initiator on the secondary
0: exact matching for memory read retry cycles from initiator on the
secondary interface
1: alias MEMRL or MEMRM to MEMR for memory read retry
cycles from initiator on the secondary interface
Reset to 0
Controls PI7C8150’s detection mechanism for matching non-posted
memory write retry cycles from the initiator on the primary interface
0: exact matching for non-posted memory write retry cycles from
initiator on the secondary interface
1: alias MEMWI to MEMW for non-posted memory write retry
cycles from initiator on the secondary interface
Reset to 0
Reserved. Returns 0 when read. Reset to 0.
Controls PI7C8150’s ability to enable long requests for lock cycles
0: normal lock operation
1: enable long request for lock cycle
Reset to 0
Control’s PI7C8150’s ability to enable the secondary bus to hold
requests longer.
0: internal secondary master will release REQ_L after FRAME_L
assertion
1: internal secondary master will hold REQ_L until there is no
transactions pending in FIFO or until terminated by target
Reset to 1
78
March 19, 2003 – Revision 1.04
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
PI7C8150