PI7C8150ND Pericom Semiconductor, PI7C8150ND Datasheet - Page 46

• Manufacturer Part Number: PI7C8150ND
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8150ND

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 85C
• Package Type: BGA
• Rad Hardened: No
• Case: BGA
• Dc: 04+
• Lead Free Status / Rohs Status: Not Compliant

5.2
5.3
Table 5-1. Summary of Transaction Ordering
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GENERAL ORDERING GUIDELINES
Independent transactions on primary and secondary buses have a relationship only when
those transactions cross PI7C8150.
The following general ordering guidelines govern transactions crossing PI7C8150:
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ORDERING RULES
Table 5–1 shows the ordering relationships of all the transactions and refers by number to
the ordering rules that follow.
Pass
Posted Write
Delayed Read Request
Delayed Write Request
Delayed Read
Completion
Delayed Write
Completion
PI7C8150 does not collapse sequential write transactions to the same address into a
single write transaction—the PCI Local Bus Specification does not permit this
combining of transactions.
The ordering relationship of a transaction with respect to other transactions is
determined when the transaction completes, that is, when a transaction ends with a
termination other than target retry.
Requests terminated with target retry can be accepted and completed in any order with
respect to other transactions that have been terminated with target retry. If the order of
completion of delayed requests is important, the initiator should not start a second
delayed transaction until the first one has been completed. If more than one delayed
transaction is initiated, the initiator should repeat all delayed transaction requests,
using some fairness algorithm. Repeating a delayed transaction cannot be contingent
on completion of another delayed transaction. Otherwise, a deadlock can occur.
Write transactions flowing in one direction have no ordering requirements with respect
to write transactions flowing in the other direction. PI7C8150 can accept posted write
transactions on both interfaces at the same time, as well as initiate posted write
transactions on both interfaces at the same time.
The acceptance of a posted memory write transaction as a target can never be
contingent on the completion of a non-locked, non-posted transaction as a master. This
is true for PI7C81500 and must also be true for other bus agents. Otherwise, a
deadlock can occur.
PI7C8150 accepts posted write transactions, regardless of the state of completion of
any delayed transactions being forwarded across PI7C8150.
Posted
Write
No
No
No
No
Yes
1
2
4
3
36
Delayed
Read
Request
Yes
No
No
Yes
Yes
5
Delayed
Write
Request
Yes
No
No
Yes
Yes
5
March 19, 2003 – Revision 1.04
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
Delayed Read
Completion
Yes
Yes
Yes
No
No
5
Delayed Write
Completion
Yes
Yes
Yes
No
No
5
PI7C8150